8.3 Do's and Don'ts

When using the LMG1210, DO:

1. Read and fully understand the data sheet, including the application notes and layout recommendations.
2. Use a four-layer board and place the return power path on an inner layer to minimize power-loop inductance.
3. Use small, surface-mount bypass and bus capacitors to minimize parasitic inductance.
4. Use the proper size decoupling capacitors and place them close to the IC as described in the Layout Guidelines section.
5. Use common-mode chokes for the input signals to reduce ground bounce noise. If not, ensure the signal source is connected to the signal V_SS plane which is tied to the power source only at the LMG1210 IC.

To avoid issues in your system when using the LMG1210, DON'T:

1. Use a single-layer or two-layer PCB for the LMG1210 as the power-loop and bypass capacitor inductances will be excessive and prevent proper operation of the IC.
2. Reduce the bypass capacitor values below the recommended values.
3. Allow the device to experience pin transients above 200 V as they may damage the device.
4. Drive the IC from a controller with a separate ground connection than the V_SS pin of the IC, unless connecting though a CMC.