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6.9 Timing Requirements

			MIN	NOM	MAX	UNIT
DEVICE (Sampling) CLOCK (CLK+, CLK–)
f_CLK	Input clock frequency (CLK+, CLK–), both single-channel and dual-channel modes⁽¹⁾		800		3200	MHz
SYSREF (SYSREF+, SYSREF–)
t_INV(SYSREF)	Width of invalid SYSREF capture region of CLK± period, indicating setup or hold time violation, as measured by the SYSREF_POS status register⁽²⁾			48		ps
t_INV(TEMP)	Drift of invalid SYSREF capture region over temperature, positive number indicates a shift toward the MSB of the SYSREF_POS register			0		ps/°C
t_INV(VA11)	Drift of invalid SYSREF capture region over the VA11 supply voltage, positive number indicates a shift toward the MSB of the SYSREF_POS register			0.36		ps/mV
t_STEP(SP)	Delay of the SYSREF_POS LSB	SYSREF_ZOOM = 0		77		ps
t_STEP(SP)	Delay of the SYSREF_POS LSB	SYSREF_ZOOM = 1		24		ps
t_{(PH_SYS)}	Minimum SYSREF± assertion duration after a SYSREF± rising edge event			4		ns
t_{(PL_SYS)}	Minimum SYSREF± de-assertion duration after a SYSREF± falling edge event			1		ns
JESD204B SYNC TIMING (SYNCSE or TMSTP±)
t_H(SYNCSE)	Minimum hold time from a multiframe boundary (SYSREF rising edge captured high) to de-assertion of the JESD204B SYNC signal (SYNCSE if SYNC_SEL = 0 or TMSTP± if SYNC_SEL = 1) for NCO synchronization (NCO_SYNC_ILA = 1)	JMODE = 4 or 6		21		t_CLK cycles
		JMODE = 5 or 7		17
		JMODE = 17 or 18		9
t_SU(SYNCSE)	Minimum setup time from de-assertion of the JESD204B SYNC signal (SYNCSE if SYNC_SEL = 0 or TMSTP± if SYNC_SEL = 1) to multiframe boundary (SYSREF rising edge captured high) for NCO synchronization (NCO_SYNC_ILA = 1)	JMODE = 4 or 6		–2		t_CLK cycles
		JMODE = 5 or 7		2
		JMODE = 17 or 18		10
t_(SYNCSE)	SYNCSE minimum assertion time to trigger link resynchronization			4		Frames
SERIAL PROGRAMMING INTERFACE (SCLK, SDI, SCS)
f_CLK(SCLK)	Maximum serial clock frequency			15.625		MHz
t_(PH)	Minimum serial clock high value pulse duration			32		ns
t_(PL)	Minimum serial clock low value pulse duration			32		ns
t_SU(SCS)	Minimum setup time from SCS to rising edge of SCLK			30		ns
t_H(SCS)	Minimum hold time from rising edge of SCLK to SCS			3		ns
t_SU(SDI)	Minimum setup time from SDI to rising edge of SCLK			30		ns
t_H(SDI)	Minimum hold time from rising edge of SCLK to SDI			3		ns

(1) Unless functionally limited to a smaller range in Table 10 based on the programmed JMODE.

(2) Use SYSREF_POS to select an optimal SYSREF_SEL value for SYSREF capture, see the SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing) section for more information on SYSREF windowing. The invalid region, specified by t_INV(SYSREF), indicates the portion of the CLK± period (t_CLK), as measured by SYSREF_SEL, that may result in a setup and hold violation. Verify that the timing skew between SYSREF± and CLK± over system operating conditions from the nominal conditions (that used to find optimal SYSREF_SEL) does not result in the invalid region occurring at the selected SYSREF_SEL position in SYSREF_POS, otherwise a temperature-dependent SYSREF_SEL selection may be needed to track the skew between CLK± and SYSREF±.