8.4.1.1 Stand-Alone Operation

The serial clock SCLK can be a continuous or a gated clock. When SYNC is high, the SCLK and SDIN signals are blocked and the SDO pin is in a HiZ state. Exactly 24 falling clock edges must be applied before SYNC is brought high. If SYNC is brought high before the 24th falling SCLK edge, then the data written are not transferred into the internal registers. If more than 24 falling SCLK edges are applied before SYNC is brought high, then the last 24 bits are used. The device internal registers are updated from the Shift Register on the rising edge of SYNC. In order for another serial transfer to take place, SYNC must be brought low again.