ZHCSHR4F January   2009  – April 2018 DAC7568 , DAC8168 , DAC8568

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     框图
  4. 4 修订历史记录
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Electrical Characteristics
    3. 7.3 Timing Requirements
    4. 7.4 Typical Characteristics: Internal Reference
    5. 7.5 Typical Characteristics: DAC at AVDD = 5.5 V
    6. 7.6 Typical Characteristics: DAC at AVDD = 3.6 V
    7. 7.7 Typical Characteristics: DAC at AVDD = 2.7 V
  8. 8 Detailed Description
    1. 8.1 Functional Block Diagram
    2. 8.2 Feature Description
      1. 8.2.1  Digital-to-Analog Converter (DAC)
      2. 8.2.2  Resistor String
      3. 8.2.3  Output Amplifier
      4. 8.2.4  Internal Reference
      5. 8.2.5  Serial Interface
      6. 8.2.6  Input Shift Register
        1. Table 1. DAC8568 Data Input Register Format
        2. Table 2. DAC8168 Data Input Register Format
        3. Table 3. DAC7568 Data Input Register Format
      7. 8.2.7  SYNC Interrupt
      8. 8.2.8  Power-on Reset to Zero Scale or Midscale
      9. 8.2.9  Clear Code Register and CLR Pin
      10. 8.2.10 Software Reset Function
      11. 8.2.11 Operating Examples: DAC7568/DAC8168/DAC8568
        1. Table 4.   1st: Write to Data Buffer A:
        2. Table 5.   2nd: Write to Data Buffer B:
        3. Table 6.   3rd: Write to Data Buffer G:
        4. Table 7.   4th: Write to Data Buffer H and Simultaneously Update all DACs:
        5. Table 8.   1st: Write to Data Buffer C and Load DAC C: DAC C Output Settles to Specified Value Upon Completion:
        6. Table 9.   2nd: Write to Data Buffer D and Load DAC D: DAC D Output Settles to Specified Value Upon Completion:
        7. Table 10. 3rd: Write to Data Buffer E and Load DAC E: DAC E Output Settles to Specified Value Upon Completion:
        8. Table 11. 4th: Write to Data Buffer F and Load DAC F: DAC F Output Settles to Specified Value Upon Completion:
        9. Table 12. 1st: Write Power-Down Command to DAC Channel A and DAC Channel B: DAC A and DAC B to 1kΩ.
        10. Table 13. 2nd: Write Power-Down Command to DAC Channel H: DAC H to 1kΩ.
        11. Table 14. 3rd: Write Power-Down Command to DAC Channel C and DAC Channel D: DAC C and DAC D to 100kΩ.
        12. Table 15. 4th: Write Power-Down Command to DAC Channel F: DAC F to 100kΩ.
        13. Table 16. 1st: Write Sequence for Enabling the DAC7568, DAC8168, and DAC8568 Internal Reference All the Time:
        14. Table 17. 2nd: Write Sequence to Power-Down All DACs to High-Impedance:
        15. Table 18. 1st: Write Sequence for Disabling the DAC7568, DAC8168, and DAC8568 Internal Reference All the Time (after this sequence, these devices require an external reference source to function):
        16. Table 19. 2nd: Write Sequence to Write Specified Data to All DACs:
    3. 8.3 Device Functional Modes
      1. 8.3.1 Enable/Disable Internal Reference
        1. 8.3.1.1 Static Mode
          1. Table 20. Write Sequence for Enabling Internal Reference (Static Mode) (Internal Reference Powered On—08000001h)
          2. Table 21. Write Sequence for Disabling Internal Reference (Static Mode) (Internal Reference Powered On—08000000h)
        2. 8.3.1.2 Flexible Mode
          1. Table 22. Write Sequence for Enabling Internal Reference (Flexible Mode) (Internal Reference Powered On—09080000h)
          2. Table 23. Write Sequence for Enabling Internal Reference (Flexible Mode) (Internal Reference Always Powered On—090A0000h)
          3. Table 24. Write Sequence for Disabling Internal Reference (Flexible Mode) (Internal Reference Always Powered Down—090C0000h)
          4. Table 25. Write Sequence for Switching from Flexible Mode to Static Mode for Internal Reference (Internal Reference Always Powered Down—09000000h)
      2. 8.3.2 LDAC Functionality
      3. 8.3.3 Power-Down Modes
        1. 8.3.3.1 DAC Power-Down Commands
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications - Microprocessor Interfacing
      1. 9.2.1 DAC7568/DAC8168/DAC8568 to an 8051 Interface
        1. 9.2.1.1 Detailed Design Procedure
          1. 9.2.1.1.1 Internal Reference
            1. 9.2.1.1.1.1 Supply Voltage
            2. 9.2.1.1.1.2 Temperature Drift
            3. 9.2.1.1.1.3 Noise Performance
            4. 9.2.1.1.1.4 Load Regulation
            5. 9.2.1.1.1.5 Long-Term Stability
            6. 9.2.1.1.1.6 Thermal Hysteresis
          2. 9.2.1.1.2 DAC Noise Performance
          3. 9.2.1.1.3 Bipolar Operation Using The DAC7568/DAC8168/DAC8568
      2. 9.2.2 DAC7568/DAC8168/DAC8568 to Microwire Interface
      3. 9.2.3 DAC7568/DAC8168/DAC8568 to 68HC11 Interface
  10. 10Layout
    1. 10.1 Layout Guidelines
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 器件命名规则
        1. 11.1.1.1 静态性能
          1. 11.1.1.1.1  分辨率
          2. 11.1.1.1.2  最低有效位 (LSB)
          3. 11.1.1.1.3  最高有效位 (MSB)
          4. 11.1.1.1.4  相对精度或积分非线性 (INL)
          5. 11.1.1.1.5  微分非线性 (DNL)
          6. 11.1.1.1.6  满量程误差
          7. 11.1.1.1.7  偏移误差
          8. 11.1.1.1.8  零代码误差
          9. 11.1.1.1.9  增益误差
          10. 11.1.1.1.10 满量程误差漂移
          11. 11.1.1.1.11 偏移误差漂移
          12. 11.1.1.1.12 零代码误差漂移
          13. 11.1.1.1.13 增益温度系数
          14. 11.1.1.1.14 电源抑制比 (PSRR)
          15. 11.1.1.1.15 单调性
        2. 11.1.1.2 动态性能
          1. 11.1.1.2.1  压摆率
          2. 11.1.1.2.2  输出电压稳定时间
          3. 11.1.1.2.3  代码更改/数模转换毛刺脉冲能量
          4. 11.1.1.2.4  数字馈通
          5. 11.1.1.2.5  通道到通道直流串扰
          6. 11.1.1.2.6  通道到通道交流串扰
          7. 11.1.1.2.7  信噪比 (SNR)
          8. 11.1.1.2.8  总谐波失真 (THD)
          9. 11.1.1.2.9  无杂散动态范围 (SFDR)
          10. 11.1.1.2.10 信噪比和失真率 (SINAD)
          11. 11.1.1.2.11 DAC 输出噪声密度
          12. 11.1.1.2.12 DAC 输出噪声
          13. 11.1.1.2.13 满量程范围 (FSR)
    2. 11.2 相关链接
    3. 11.3 接收文档更新通知
    4. 11.4 社区资源
    5. 11.5 商标
    6. 11.6 静电放电警告
    7. 11.7 Glossary
  12. 12机械、封装和可订购信息

8.2.8 Power-on Reset to Zero Scale or Midscale

The DAC7568, DAC8168, and DAC8568 contain a power-on reset circuit that controls the output voltage during power-up. For device grades A and C on power-up, all DAC registers are filled with zeros and the output voltages of all DAC channels are set to zero scale. For device grades B and D all DAC registers are set to have all DAC channels power up in midscale. All DAC channels remain that way until a valid write sequence and load command are made to the respective DAC channel. The power-on reset is useful in applications where it is important to know the state of the output of each DAC while the device is in the process of powering up. No device pin should be brought high before power is applied to the device. The internal reference is powered off / down by default and remains that way until a valid reference-change command is executed.
千亿体育app官网登录(中国)官方网站IOS/安卓通用版/手机APP | 米乐app下载官网（中国）|ios|Android/通用版APP最新版 | 米乐|米乐·M6（中国大陆）官方网站 | 千亿体育登陆地址 | 华体会体育（中国）HTH·官方网站 | 千赢qy国际_全站最新版千赢qy国际V6.2.14安卓/IOS下载 | 18新利网v1.2.5|中国官方网站 | bob电竞真人（中国官网）安卓/ios苹果/电脑版【1.97.95版下载】 | 千亿体育app官方下载(中国)官方网站IOS/安卓/手机APP下载安装 |