ZHCSHR4F January   2009  – April 2018 DAC7568 , DAC8168 , DAC8568

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     框图
  4. 4 修订历史记录
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Electrical Characteristics
    3. 7.3 Timing Requirements
    4. 7.4 Typical Characteristics: Internal Reference
    5. 7.5 Typical Characteristics: DAC at AVDD = 5.5 V
    6. 7.6 Typical Characteristics: DAC at AVDD = 3.6 V
    7. 7.7 Typical Characteristics: DAC at AVDD = 2.7 V
  8. 8 Detailed Description
    1. 8.1 Functional Block Diagram
    2. 8.2 Feature Description
      1. 8.2.1  Digital-to-Analog Converter (DAC)
      2. 8.2.2  Resistor String
      3. 8.2.3  Output Amplifier
      4. 8.2.4  Internal Reference
      5. 8.2.5  Serial Interface
      6. 8.2.6  Input Shift Register
        1. Table 1. DAC8568 Data Input Register Format
        2. Table 2. DAC8168 Data Input Register Format
        3. Table 3. DAC7568 Data Input Register Format
      7. 8.2.7  SYNC Interrupt
      8. 8.2.8  Power-on Reset to Zero Scale or Midscale
      9. 8.2.9  Clear Code Register and CLR Pin
      10. 8.2.10 Software Reset Function
      11. 8.2.11 Operating Examples: DAC7568/DAC8168/DAC8568
        1. Table 4.   1st: Write to Data Buffer A:
        2. Table 5.   2nd: Write to Data Buffer B:
        3. Table 6.   3rd: Write to Data Buffer G:
        4. Table 7.   4th: Write to Data Buffer H and Simultaneously Update all DACs:
        5. Table 8.   1st: Write to Data Buffer C and Load DAC C: DAC C Output Settles to Specified Value Upon Completion:
        6. Table 9.   2nd: Write to Data Buffer D and Load DAC D: DAC D Output Settles to Specified Value Upon Completion:
        7. Table 10. 3rd: Write to Data Buffer E and Load DAC E: DAC E Output Settles to Specified Value Upon Completion:
        8. Table 11. 4th: Write to Data Buffer F and Load DAC F: DAC F Output Settles to Specified Value Upon Completion:
        9. Table 12. 1st: Write Power-Down Command to DAC Channel A and DAC Channel B: DAC A and DAC B to 1kΩ.
        10. Table 13. 2nd: Write Power-Down Command to DAC Channel H: DAC H to 1kΩ.
        11. Table 14. 3rd: Write Power-Down Command to DAC Channel C and DAC Channel D: DAC C and DAC D to 100kΩ.
        12. Table 15. 4th: Write Power-Down Command to DAC Channel F: DAC F to 100kΩ.
        13. Table 16. 1st: Write Sequence for Enabling the DAC7568, DAC8168, and DAC8568 Internal Reference All the Time:
        14. Table 17. 2nd: Write Sequence to Power-Down All DACs to High-Impedance:
        15. Table 18. 1st: Write Sequence for Disabling the DAC7568, DAC8168, and DAC8568 Internal Reference All the Time (after this sequence, these devices require an external reference source to function):
        16. Table 19. 2nd: Write Sequence to Write Specified Data to All DACs:
    3. 8.3 Device Functional Modes
      1. 8.3.1 Enable/Disable Internal Reference
        1. 8.3.1.1 Static Mode
          1. Table 20. Write Sequence for Enabling Internal Reference (Static Mode) (Internal Reference Powered On—08000001h)
          2. Table 21. Write Sequence for Disabling Internal Reference (Static Mode) (Internal Reference Powered On—08000000h)
        2. 8.3.1.2 Flexible Mode
          1. Table 22. Write Sequence for Enabling Internal Reference (Flexible Mode) (Internal Reference Powered On—09080000h)
          2. Table 23. Write Sequence for Enabling Internal Reference (Flexible Mode) (Internal Reference Always Powered On—090A0000h)
          3. Table 24. Write Sequence for Disabling Internal Reference (Flexible Mode) (Internal Reference Always Powered Down—090C0000h)
          4. Table 25. Write Sequence for Switching from Flexible Mode to Static Mode for Internal Reference (Internal Reference Always Powered Down—09000000h)
      2. 8.3.2 LDAC Functionality
      3. 8.3.3 Power-Down Modes
        1. 8.3.3.1 DAC Power-Down Commands
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications - Microprocessor Interfacing
      1. 9.2.1 DAC7568/DAC8168/DAC8568 to an 8051 Interface
        1. 9.2.1.1 Detailed Design Procedure
          1. 9.2.1.1.1 Internal Reference
            1. 9.2.1.1.1.1 Supply Voltage
            2. 9.2.1.1.1.2 Temperature Drift
            3. 9.2.1.1.1.3 Noise Performance
            4. 9.2.1.1.1.4 Load Regulation
            5. 9.2.1.1.1.5 Long-Term Stability
            6. 9.2.1.1.1.6 Thermal Hysteresis
          2. 9.2.1.1.2 DAC Noise Performance
          3. 9.2.1.1.3 Bipolar Operation Using The DAC7568/DAC8168/DAC8568
      2. 9.2.2 DAC7568/DAC8168/DAC8568 to Microwire Interface
      3. 9.2.3 DAC7568/DAC8168/DAC8568 to 68HC11 Interface
  10. 10Layout
    1. 10.1 Layout Guidelines
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 器件命名规则
        1. 11.1.1.1 静态性能
          1. 11.1.1.1.1  分辨率
          2. 11.1.1.1.2  最低有效位 (LSB)
          3. 11.1.1.1.3  最高有效位 (MSB)
          4. 11.1.1.1.4  相对精度或积分非线性 (INL)
          5. 11.1.1.1.5  微分非线性 (DNL)
          6. 11.1.1.1.6  满量程误差
          7. 11.1.1.1.7  偏移误差
          8. 11.1.1.1.8  零代码误差
          9. 11.1.1.1.9  增益误差
          10. 11.1.1.1.10 满量程误差漂移
          11. 11.1.1.1.11 偏移误差漂移
          12. 11.1.1.1.12 零代码误差漂移
          13. 11.1.1.1.13 增益温度系数
          14. 11.1.1.1.14 电源抑制比 (PSRR)
          15. 11.1.1.1.15 单调性
        2. 11.1.1.2 动态性能
          1. 11.1.1.2.1  压摆率
          2. 11.1.1.2.2  输出电压稳定时间
          3. 11.1.1.2.3  代码更改/数模转换毛刺脉冲能量
          4. 11.1.1.2.4  数字馈通
          5. 11.1.1.2.5  通道到通道直流串扰
          6. 11.1.1.2.6  通道到通道交流串扰
          7. 11.1.1.2.7  信噪比 (SNR)
          8. 11.1.1.2.8  总谐波失真 (THD)
          9. 11.1.1.2.9  无杂散动态范围 (SFDR)
          10. 11.1.1.2.10 信噪比和失真率 (SINAD)
          11. 11.1.1.2.11 DAC 输出噪声密度
          12. 11.1.1.2.12 DAC 输出噪声
          13. 11.1.1.2.13 满量程范围 (FSR)
    2. 11.2 相关链接
    3. 11.3 接收文档更新通知
    4. 11.4 社区资源
    5. 11.5 商标
    6. 11.6 静电放电警告
    7. 11.7 Glossary
  12. 12机械、封装和可订购信息

8.3.3.1 DAC Power-Down Commands

The DAC7568, DAC8168, and DAC8568 use four modes of operation. These modes are accessed by setting control bits C3, C2, C1, and C0, and power-down register bits DB8 and DB9. The control bits must be set to '0100'. Once the control bits are set correctly, the four different power down modes are software programmable by setting bits DB8 and DB9 in the control register. and Table 4 shows how to control the operating mode with data bits PD0 (DB8), and PD1 (DB9).

Table 4. DAC Operating Modes

PD1
(DB9)		 PD0
(DB8)		 DAC OPERATING MODES
0 0 Power up selected DACs
0 1 Power down selected DACs 1kΩ to GND
1 0 Power down selected DACs 100kΩ to GND
1 1 Power down selected DACs High-Z to GND

The DAC7568, DAC8168, and DAC8568 treat the power-down condition as data; all the operational modes are still valid for power-down. It is possible to broadcast a power-down condition to all the DAC8568, DAC8168, DAC7568s in a system. It is also possible to power-down a channel and update data on other channels. Furthermore, it is possible to write to the DAC register/buffer of the DAC channel that is powered down. When the DAC channel is then powered up, it will power up to this new value (see the Operating Examples section).

When both the PD0 and PD1 bits are set to '0', the device works normally with its typical current consumption of 1.25mA at 5.5V. The reference current is included with the operation of all eight DACs. However, for the three power-down modes, the supply current falls to 0.18μA at 5.5V (0.10μA at 3.6V). Not only does the supply current fall, but the output stage also switches internally from the output of the amplifier to a resistor network of known values.

The advantage of this switching is that the output impedance of the device is known while it is in power-down mode. As described in Table 4, there are three different power-down options. VOUT can be connected internally to GND through a 1kΩ resistor, a 100kΩ resistor, or open circuited (High-Z). The output stage is shown in Figure 124. In other words, DB27, DB26, DB25, and DB24 = '0100' and DB9 and DB8 = '11' represent a power-down condition with High-Z output impedance for a selected channel. DB9 and DB8 = '01' represents a power-down condition with 1kΩ output impedance, and '10' represents a power-down condition with 100kΩ output impedance.

DAC7568 DAC8168 DAC8568 too_out_stage_bas403.gifFigure 124. Output Stage During Power-Down

All analog channel circuits are shut down when the power-down mode is exercised. However, the contents of the DAC register are unaffected when in power down. By setting both bits, DB8 and DB9, to different values, any combination of DAC channels can be powered down or powered up. If a DAC channel is being powered up from a previously power down situation, this DAC channel powers up to the value in its DAC register. The time required to exit power-down is typically 2.5μs for AVDD = 5V, and 4μs for AVDD = 3V. See the Typical Characteristics section for more information.
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