米6体育平台手机版

ZHCSHR5C March 2018 – September 2019 TUSB1064

PRODUCTION DATA.

6.5 ELECTRICAL CHARACTERISTICS

over operating free-air temperature and voltage range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
Power
P_{CC-ACTIVE-USB}	Average active power in USB-only mode while in U0.	CTL1 = L; CTL0 = H; Link in U0 at 10Gbps;		330		mW
P_{CC-ACTIVE-USB-DP}	Average active power in USB + 2 lane DP mode.	CTL1 = H; CTL0 = H; USB in U0 at 10Gbps; DP at 8.1Gbps;		660		mW
P_CC-ACTIVE-DP	Average active power in 4 lane DP mode.	CTL1 = H; CTL0 = L; Four DP lanes at 8.1Gbps		660		mW
P_CC-NC-USB	Average power in USB mode while in disconnect state.	CTL1 = L; CTL0 = H; No USB device detected;		2.5		mW
P_CC-U2U3	Average power in USB mode while in U2/U3 state	CTL1 = L; CTL0 = H; Link in U2 or U3;		2.5		mW
P_CC-SHUTDOWN	Average power in Shutdown mode.	CTL1 = L; CTL0 = L; I2C_EN = "0";		0.7		mW
4-State CMOS Inputs(EQ[1:0], SSEQ[1:0], DPEQ[1:0], I2C_EN)
I_IH	High-level input current	V_CC = 3.6 V; V_IN = 3.6 V	20		80	µA
I_IL	Low-level input current	V_CC = 3.6 V; V_IN = 0 V	-160		-40	µA
4-Level V_TH	Threshold 0 / R	V_CC = 3.3 V		0.55		V
	Threshold R/ Float	V_CC = 3.3 V		1.65		V
	Threshold Float / 1	V_CC = 3.3 V		2.7		V
R_PU	Internal pull up resistance			45		kΩ
R_PD	Internal pull-down resistance			95		kΩ
2-State CMOS Input (CTL0, CTL1, FLIP, EN, HPDIN) CTL1, CTL0 and FLIP are Failsafe
V_IH	High-level input voltage		2		3.6	V
V_IL	Low-level input voltage		0		0.8	V
R_PD	Internal pull-down resistance for CTL1, CTL0, FLIP, and EN.			500		kΩ
I_IH	High-level input current	V_IN = 3.6 V	-25		25	µA
I_IL	Low-level input current	V_IN = GND, V_CC = 3.6 V	-25		25	µA
I2C Control Pins SCL, SDA
V_IH	High-level input voltage	I2C_EN ! = 0	0.7 x V_I2C		3.6	V
V_IL	Low-level input voltage	I2C_EN ! = 0	0		0.3 × V_I2C	V
V_OL	Low-level output voltage	I2C_EN ! = 0; I_OL = 3 mA	0		0.4	V
I_OL	Low-level output current	I2C_EN ! = 0; V_OL = 0.4 V	20			mA
I_{i_I2C}	Input current on SDA pin	0.1 × V_I2C < Input voltage < 3.3 V	-10		10	µA
C_{i_I2C}	Input capacitance				10	pF
USB Differential Receiver (RX1P/N, RX2P/N, SSTXP/N)
V_RX-DIFF-PP	Input differential peak-peak voltage swing linear dynamic range	AC-coupled differential peak-to-peak signal measured post CTLE through a reference channel		2000		mVpp
V_RX-DC-CM	Common-mode voltage bias in the receiver (DC)			0		V
R_RX-DIFF-DC	Differential input impedance (DC)	Present after a USB3.1 device is detected on TXP/TXN	72		120	Ω
R_RX-CM-DC	Receiver DC Common Mode impedance	Present after a USB3.1 device is detected on TXP/TXN	18		30	Ω
Z_{RX-HIGH-IMP-DC-POS}	Common-mode input impedance with termination disabled (DC)	Present when no USB3.1 device is detected on TXP/TXN. Measured over the range of 0-500 mV with respect to GND.	25			kΩ
V_{SIGNAL-DET-DIFF-PP}	Input Differential peak-to-peak Signal Detect Assert Level	at 10Gbps, No loss and bit rate PRBS7 pattern		79		mV
V_{RX-IDLE-DET-DIFF-PP}	Input Differential peak-to-peak Signal Detect De-assert Level	at 10 Gbps, No loss and bit rate PRBS7 pattern		58		mV
V_{RX-LFPS-DET-DIFF-PP}	Low-frequency Periodic Signaling (LFPS) Detect Threshold	Below the minimum is squelched.	100		300	mV
C_RX	RX input capacitance to GND	At 2.5 GHz		0.5	1	pF
RL_RX-DIFF	Differential Return Loss	50 MHz – 1.25 GHz at 90 Ω		-13		dB
RL_RX-DIFF	Differential Return Loss	5 GHz at 90 Ω		-9		dB
RL_RX-CM	Common Mode Return Loss	50 MHz – 5 GHz at 90 Ω		-8		dB
EQ_SSP	Receiver equalization	SSEQ[1:0] and EQ[1:0] at 5 GHz.		12		dB
USB Differential Transmitter (TX1P/N, TX2P/N, SSRXP/N)
V_TX-DIFF-PP	Transmitter dynamic differential voltage swing range.			1300		mVpp
V_{TX-RCV-DETECT}	Amount of voltage change allowed during Receiver Detection	at 3.3 V			600	mV
V_{TX-CM-IDLE-DELTA}	Transmitter idle common-mode voltage change while in U2/U3 and not actively transmitting LFPS	measured at the connector side of the AC coupling caps with 50 Ω load	-600		600	mV
V_TX-DC-CM	Common-mode voltage bias in the transmitter (DC)		0		2	V
V_{TX-CM-AC-PP-ACTIVE}	Tx AC Common-mode voltage active	At 3.3V; Max mismatch from Txp+Txn for both time and amplitude			100	mVpp
V_{TX-IDLE-DIFF-AC-PP}	AC Electrical idle differential peak-to-peak output voltage	At package pins	0		10	mV
V_{TX-IDLE-DIFF-DC}	DC Electrical idle differential output voltage	At package pins after low-pass filter to remove AC component	0		14	mV
V_{TX-CM-DC-ACTIVE-IDLE-DELTA}	Absolute DC common mode voltage between U1 and U0	At package pin			200	mV
C_TX	TX input capacitance to GND	At 2.5 GHz			1.25	pF
R_TX-DIFF	Differential impedance of the driver		75		120	Ω
C_AC-COUPLING	AC Coupling capacitor		75		265	nF
R_TX-CM	Common-mode impedance of the driver	Measured with respect to AC ground over 0-500 mV	18		30	Ω
I_TX-SHORT	TX short circuit current	TX+/- shorted to GND			67	mA
RL_TX-DIFF	Differential Return Loss	50 MHz – 1.25 GHz at 90 Ω		-17		dB
RL_TX-DIFF-5G	Differential Return Loss	5 GHz at 90 Ω		-12		dB
RL_TX-CM	Common Mode Return Loss	50 MHz – 5 GHz at 90 Ω		-9		dB
AC Electrical Characteristics for USB and DP
Crosstalk	Differential Cross Talk between TX and RX signal Pairs	at 5 GHz		-27		dB
G_LF	Low-frequency voltage gain.	at 100 MHz, 600 mVpp V_ID	-2.5	0.5	3.5	dB
G_{LF_LFPS_TX1/2}	Low-frequency voltage gain for SSTX->TX1/TX2 path.	at 10 to 50MHz sine wave; 1.0Vpp V_ID; EQ = 0; FLIP = 0 and 1;	0	0.8	1.6	dB
CP_{1 dB-LF}	Low-frequency 1-dB compression point	at 100 MHz, 200 mVpp < V_ID < 2000 mVpp		1000		mVpp
CP_{1 dB-HF}	High-frequency 1-dB compression point	at 5 GHz, 200 mVpp < V_ID < 2000 mVpp		770		mVpp
f_LF	Low-frequency cutoff	200 mVpp < V_ID < 2000 mVpp		20	50	kHz
D_{J_10G}	TX output deterministic jitter	200 mVpp < V_ID < 2000 mVpp, PRBS7, 10 Gbps		0.10		UIpp
D_{J_8.1G}	TX output deterministic jitter	200 mVpp < V_ID < 2000 mVpp, PRBS7, 8.1 Gbps		0.08		UIpp
T_{J_10G}	TX output total jitter	200 mVpp < V_ID < 2000 mVpp, PRBS7, 10 Gbps		0.13		UIpp
T_{J_8.1G}	TX output total jitter	200 mVpp < V_ID < 2000 mVpp, PRBS7, 8.1 Gbps		0.12		UIpp
DisplayPort Receiver (TX1P/N, TX2P/N, RX1P/N, RX2P/N)
V_{ID_PP}	Peak-to-peak input differential dynamic voltage range			2000		mV
V_IC	Input Common Mode Voltage			0		V
C_AC	AC coupling capacitance		75		265	nF
EQ_DP	Receiver Equalizer	DPEQ1, DPEQ0 at 4.05 GHz		12		dB
d_R	Data rate	HBR3			8.1	Gbps
R_ti	Input Termination resistance		80	100	120	Ω
DisplayPort Transmitter (DP[3:0]P/N)
V_TX-DIFFPP	VOD dynamic range			1300		mV
I_TX-SHORT	TX short circuit current	TX+/- shorted to GND			67	mA
AUXP/N and SBU1/2
R_ON	Output ON resistance	V_CC = 3.3 V; V_IN = 0 to 0.4 V for AUXP; V_IN = 2.7 V to 3.6 V for AUXN		5	10	Ω
R_ON-MISMATCH	ΔON resistance mismatch within pair	V_CC = 3.3 V; V_IN = 0 to 0.4 V for AUXP; V_IN= 2.7 V to 3.6 V for AUXN			1	Ω
R_{ON_FLAT}	ON resistance flatness (RONmax–RON min) measured at identical VCC and temperature	V_CC = 3.3 V; V_IN = 0 to 0.4 V for AUXP; V_IN = 2.7 V to 3.6 V for AUXN			2	Ω
V_{AUXP_DC_CM}	AUX Channel DC common mode voltage for AUXP and SBU2.	V_CC = 3.3 V	0		0.4	V
V_{AUXN_DC_CM}	AUX Channel DC common mode voltage for AUXN and SBU1	V_CC = 3.3 V	2.7		3.6	V
C_{AUX_ON}	ON-state capacitance	V_CC = 3.3 V; CTL1 = 1; V_IN = 0 V or 3.3 V		4	7	pF
C_{AUX_OFF}	OFF-state capacitance	V_CC = 3.3 V; CTL1 = 0; V_IN = 0 V or 3.3 V		3	6	pF