The device contains a delay adjustment on the device clock (sampling clock) input path, called t_AD adjust, that can be used to shift the sampling instance within the device in order to align sampling instances among multiple devices or for external interleaving of multiple devices. Further, t_AD adjust can be used for automatic SYSREF calibration to simplify synchronization; see the Automatic SYSREF Calibration section. Aperture delay adjustment is implemented in a way that adds no additional noise to the clock path; however, a slight degradation in aperture jitter (t_AJ) is possible at large values of TAD_COARSE because of internal clock path attenuation. The degradation in aperture jitter can result in minor SNR degradations at high input frequencies (see t_AJ in the Switching Characteristics table). This feature is programmed using TAD_INV, TAD_COARSE, and TAD_FINE in the DEVCLK timing adjust ramp control register. Setting TAD_INV inverts the input clock resulting in a delay equal to half the clock period. Table 6-5 summarizes the step sizes and ranges of the TAD_COARSE and TAD_FINE variable analog delays. All three delay options are independent and can be used in conjunction. All clocks within the device are shifted by the programmed t_AD adjust amount, which results in a shift of the timing of the JESD204C serialized outputs and affects the capture of SYSREF.

In order to maintain timing alignment between converters, stable and matched power-supply voltages and device temperatures must be provided.

Aperture delay adjustment can be changed on-the-fly during normal operation but may result in brief upsets to the JESD204C data link. Use TAD_RAMP to reduce the probability of the JESD204C link losing synchronization; see the Aperture Delay Ramp Control section.