The FIFO_ALM bit indicates if an underflow or overflow condition has occurred on any of the JESD204C serializer lanes within the synchronizing FIFO between the digital logic block and serializer outputs. The FIFO_LANE_ALM register bits can be used to determine which lane triggered the underflow or overflow condition alarm. If the FIFO pointers are upset due to an undesired clock shift or other single event or incorrect clocking frequencies the FIFO_LANE_ALM bit for the erroneous lane will be set to 1. If the INIT_ON_FIFO_ALM bit is set then the serializers, FIFO and JESD204C block will automatically reinitialize.