For the system gain management to have the best possible response time, a low-latency configurable overrange function is included. The overrange function works by monitoring the converted 12-bit samples at the ADC to quickly detect if the ADC is near saturation or already in an overrange condition. The absolute value of the upper 8 bits of the ADC data are checked against two programmable thresholds, OVR_T0 and OVR_T1. These thresholds apply to both channel A and channel B in dual-channel mode. Table 7-1 lists how an ADC sample is converted to an absolute value for a comparison of the thresholds.

If the upper 8 bits of the absolute value equal or exceed the OVR_T0 or OVR_T1 thresholds during the monitoring period, then the overrange bit associated with the threshold is set to 1, otherwise the overrange bit is 0. In dual-channel mode, the overrange status can be monitored on the ORA0 and ORA1 pins for channel A and the ORB0 and ORB1 pins for channel B, where ORx0 corresponds to the OVR_T0 threshold and ORx1 corresponds to the OVR_T1 threshold. In single-channel mode, the overrange status for the OVR_T0 threshold is determined by monitoring both the ORA0 and ORB0 outputs and the OVR_T1 threshold is determined by monitoring both ORA1 and ORB1 outputs. In single-channel mode, the two outputs for each threshold must be OR'd together to determine whether an overrange condition occurred. OVR_N can be used to set the output pulse duration from the last overrange event.Table 7-2 lists the overrange pulse lengths for the various OVR_N settings (see the overrange configuration register). In decimation modes (only in the JMODEs where CS = 1 in JESD204C Operating Modes Table), the overrange status is also embedded into the output data samples where the OVR_T0 threshold status is embedded as the LSB along with the upper 15 bits of every complex I sample and the OVR_T1 threshold status is embedded as the LSB along with the upper 15 bits of every complex Q sample. Table 7-3 lists the outputs, related data samples, threshold settings, and the monitoring period equation. The embedded overrange bit goes high if the associated channel exceeds the associated overrange threshold within the monitoring period set by OVR_N. Use Table 7-3 to calculate the monitoring period.

Typically, the OVR_T0 threshold can be set near the full-scale value (228 for example). When the threshold is triggered, a typical system can turn down the system gain to avoid clipping. The OVR_T1 threshold can be set much lower. For example, the OVR_T1 threshold can be set to 64 (peak input voltage of −12 dBFS). If the input signal is strong, the OVR_T1 threshold is tripped occasionally. If the input is quite weak, the threshold is never tripped. The downstream logic device monitors the OVR_T1 bit. If OVR_T1 stays low for an extended period of time, then the system gain can be increased until the threshold is occasionally tripped (meaning the peak level of the signal is above −12 dBFS).