ZHCSHT9C August   2021  – June 2024 ADC12DJ4000RF

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: DC Specifications
    6. 6.6  Electrical Characteristics: Power Consumption
    7. 6.7  Electrical Characteristics: AC Specifications (Dual-Channel Mode)
    8. 6.8  Electrical Characteristics: AC Specifications (Single-Channel Mode)
    9. 6.9  Timing Requirements
    10. 6.10 Switching Characteristics
    11. 6.11 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs
        1. 7.3.1.1 Analog Input Protection
        2. 7.3.1.2 Full-Scale Voltage (VFS) Adjustment
        3. 7.3.1.3 Analog Input Offset Adjust
      2. 7.3.2 ADC Core
        1. 7.3.2.1 ADC Theory of Operation
        2. 7.3.2.2 ADC Core Calibration
        3. 7.3.2.3 Analog Reference Voltage
        4. 7.3.2.4 ADC Overrange Detection
        5. 7.3.2.5 Code Error Rate (CER)
      3. 7.3.3 Temperature Monitoring Diode
      4. 7.3.4 Timestamp
      5. 7.3.5 Clocking
        1. 7.3.5.1 Noiseless Aperture Delay Adjustment (tAD Adjust)
        2. 7.3.5.2 Aperture Delay Ramp Control (TAD_RAMP)
        3. 7.3.5.3 SYSREF Capture for Multi-Device Synchronization and Deterministic Latency
          1. 7.3.5.3.1 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
          2. 7.3.5.3.2 Automatic SYSREF Calibration
      6. 7.3.6 Programmable FIR Filter (PFIR)
        1. 7.3.6.1 Dual Channel Equalization
        2. 7.3.6.2 Single Channel Equalization
        3. 7.3.6.3 Time Varying Filter
      7. 7.3.7 Digital Down Converters (DDC)
        1. 7.3.7.1 Rounding and Saturation
        2. 7.3.7.2 Numerically-Controlled Oscillator and Complex Mixer
          1. 7.3.7.2.1 NCO Fast Frequency Hopping (FFH)
          2. 7.3.7.2.2 NCO Selection
          3. 7.3.7.2.3 Basic NCO Frequency Setting Mode
          4. 7.3.7.2.4 Rational NCO Frequency Setting Mode
          5. 7.3.7.2.5 NCO Phase Offset Setting
          6. 7.3.7.2.6 NCO Phase Synchronization
        3. 7.3.7.3 Decimation Filters
        4. 7.3.7.4 Output Data Format
        5. 7.3.7.5 Decimation Settings
          1. 7.3.7.5.1 Decimation Factor
          2. 7.3.7.5.2 DDC Gain Boost
      8. 7.3.8 JESD204C Interface
        1. 7.3.8.1  Transport Layer
        2. 7.3.8.2  Scrambler
        3. 7.3.8.3  Link Layer
        4. 7.3.8.4  8B/10B Link Layer
          1. 7.3.8.4.1 Data Encoding (8B/10B)
          2. 7.3.8.4.2 Multiframes and the Local Multiframe Clock (LMFC)
          3. 7.3.8.4.3 Code Group Synchronization (CGS)
          4. 7.3.8.4.4 Initial Lane Alignment Sequence (ILAS)
          5. 7.3.8.4.5 Frame and Multiframe Monitoring
        5. 7.3.8.5  64B/66B Link Layer
          1. 7.3.8.5.1 64B/66B Encoding
          2. 7.3.8.5.2 Multiblocks, Extended Multiblocks and the Local Extended Multiblock Clock (LEMC)
          3. 7.3.8.5.3 Block, Multiblock and Extended Multiblock Alignment using Sync Header
            1. 7.3.8.5.3.1 Cyclic Redundancy Check (CRC) Mode
            2. 7.3.8.5.3.2 Forward Error Correction (FEC) Mode
          4. 7.3.8.5.4 Initial Lane Alignment
          5. 7.3.8.5.5 Block, Multiblock and Extended Multiblock Alignment Monitoring
        6. 7.3.8.6  Physical Layer
        7. 7.3.8.7  SerDes Pre-Emphasis
        8. 7.3.8.8  JESD204C Enable
        9. 7.3.8.9  Multi-Device Synchronization and Deterministic Latency
        10. 7.3.8.10 Operation in Subclass 0 Systems
      9. 7.3.9 Alarm Monitoring
        1. 7.3.9.1 NCO Upset Detection
        2. 7.3.9.2 Clock Upset Detection
        3. 7.3.9.3 FIFO Upset Detection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Dual-Channel Mode
      2. 7.4.2 Single-Channel Mode (DES Mode)
      3. 7.4.3 Dual-Input Single-Channel Mode (DUAL DES Mode)
      4. 7.4.4 JESD204C Modes
        1. 7.4.4.1 JESD204C Operating Modes Table
        2. 7.4.4.2 JESD204C Modes continued
        3. 7.4.4.3 JESD204C Transport Layer Data Formats
        4. 7.4.4.4 64B/66B Sync Header Stream Configuration
        5. 7.4.4.5 Dual DDC and Redundant Data Mode
      5. 7.4.5 Power-Down Modes
      6. 7.4.6 Test Modes
        1. 7.4.6.1 Serializer Test-Mode Details
        2. 7.4.6.2 PRBS Test Modes
        3. 7.4.6.3 Clock Pattern Mode
        4. 7.4.6.4 Ramp Test Mode
        5. 7.4.6.5 Short and Long Transport Test Mode
          1. 7.4.6.5.1 Short Transport Test Pattern
          2. 7.4.6.5.2 Long Transport Test Pattern
        6. 7.4.6.6 D21.5 Test Mode
        7. 7.4.6.7 K28.5 Test Mode
        8. 7.4.6.8 Repeated ILA Test Mode
        9. 7.4.6.9 Modified RPAT Test Mode
      7. 7.4.7 Calibration Modes and Trimming
        1. 7.4.7.1 Foreground Calibration Mode
        2. 7.4.7.2 Background Calibration Mode
        3. 7.4.7.3 Low-Power Background Calibration (LPBG) Mode
      8. 7.4.8 Offset Calibration
      9. 7.4.9 Trimming
    5. 7.5 Programming
      1. 7.5.1 Using the Serial Interface
        1. 7.5.1.1 SCS
        2. 7.5.1.2 SCLK
        3. 7.5.1.3 SDI
        4. 7.5.1.4 SDO
        5. 7.5.1.5 Streaming Mode
    6. 7.6 SPI Register Map
  9. 8 Application Information Disclaimer
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Wideband RF Sampling Receiver
        1. 8.2.1.1 Design Requirements
          1. 8.2.1.1.1 Input Signal Path
          2. 8.2.1.1.2 Clocking
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Calculating Values of AC-Coupling Capacitors
        3. 8.2.1.3 Application Curves
    3. 8.3 Initialization Set Up
    4. 8.4 Power Supply Recommendations
      1. 8.4.1 Power Sequencing
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 接收文档更新通知
    4. 9.4 支持资源
    5. 9.5 商标
    6. 9.6 静电放电警告
    7. 9.7 术语表
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

6.6 Electrical Characteristics: Power Consumption

typical values at TA = 25°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage, fIN = 347 MHz, AIN = –1 dBFS, fCLK = 4 GHz, filtered 1-VPP sine-wave clock, JMODE = 1, Dither enabled with default settings, VA11, VD11 and VS11 noise suppression ON (EN_VA11_NOISE_SUPPR = EN_VD11_NOISE_SUPPR = EN_VS11_NOISE_SUPPR = 1), and background calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and over the operating free-air temperature range provided in the Recommended Operating Conditions table
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IVA19 1.9-V analog supply current Power mode 1: JMODE 1 (single-channel mode, 16 lanes, 8B/10B encoding, DDC bypassed), foreground calibration 927 mA
IVA11 1.1-V analog supply current 701 mA
IVD11 1.1-V digital supply current 1040 mA
PDIS Power dissipation 3.68 W
IVA19 1.9-V analog supply current Power mode 2: JMODE 30 (single-channel mode, 8 lanes, 64B/66B encoding, DDC bypassed), foreground calibration 927 1030 mA
IVA11 1.1-V analog supply current 702 850 mA
IVD11 1.1-V digital supply current 1010 1250 mA
PDIS Power dissipation 3.65 4.35 W
IVA19 1.9-V analog supply current Power mode 3: JMODE 1 (single-channel mode, 16 lanes, 8B/10B encoding, DDC bypassed), background calibration 1235 mA
IVA11 1.1-V analog supply current 845 mA
IVD11 1.1-V digital supply current 1120 mA
PDIS Power dissipation 4.60 W
IVA19 1.9-V analog supply current Power mode 4: JMODE 3 (dual-channel mode, 16 lanes, 8B/10B encoding, DDC bypassed), background calibration 1320 mA
IVA11 1.1-V analog supply current 845 mA
IVD11 1.1-V digital supply current 1025 mA
PDIS Power dissipation 4.6 W
IVA19 1.9-V analog supply current Power mode 5: JMODE 22 (single-channel mode, 8 lanes, 8B/10B encoding, 4x decimation), foreground calibration 930 mA
IVA11 1.1-V analog supply current 704 mA
IVD11 1.1-V digital supply current 1930 mA
PDIS Power dissipation 4.6 W
IVA19 1.9-V analog supply current Power mode 6: JMODE 11 (dual-channel mode, 8 lanes, 8B/10B encoding, 4x decimation), foreground calibration 1005 mA
IVA11 1.1-V analog supply current 704 mA
IVD11 1.1-V digital supply current 1850 mA
PDIS Power dissipation 4.7 W
IVA19 1.9-V analog supply current Power mode 7: PD pin held high, clock disabled 44 mA
IVA11 1.1-V analog supply current 27 mA
IVD11 1.1-V digital supply current 33 mA
PDIS Power dissipation 0.15 W
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