10.1 Layout Guidelines

A precision analog component requires careful layout, the list below provides some insight into good layout practices.

• All Power Supply pins should be bypassed to ground with a low ESR ceramic bypass capacitor. The typical recommended bypass capacitance is 0.1 to 0.22-µF ceramic with a X7R or NP0 dielectric.
• Power supplies and VREF bypass capacitors should be placed close to terminals or planes to minimize inductance and optimize performance.
• A high-quality ceramic type NP0 or X7R is recommended for its optimal performance across temperature, and very low dissipation factor.
• The digital and analog sections should have proper placement with respect to the digital pins and analog pins of the DAC9881 device. The separation of analog and digital blocks will allow for better design and practice as it will ensure less coupling into neighboring blocks, and will minimize the interaction between analog and digital return currents.