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ZHCSHV3A March 2018 – November 2018 LMX8410L

PRODUCTION DATA.

		MIN	MAX	UNIT
SYNC
t_SETUP	Setup time for pin relative to OSCIN rising edge	2.5		ns
t_HOLD	Hold time for pin relative to OSCIN rising edge	2		ns
DIGITAL WRITE INTERFACE⁽¹⁾
F_{SPI_WRITE}	SPI write speed		50	MHz
t_ES	Clock to enable low time	5		ns
t_CS	Data to clock setup time	2		ns
t_CH	Data to clock hold time	2		ns
t_CWH	Clock pulse width high	5		ns
t_CWL	Clock pulse width low	10		ns
t_CES	Enable to clock setup time	10		ns
t_EWH	Enable pulse width high	10		ns
DIGITAL READBACK INTERFACE⁽²⁾
F_{SPI_READ}	SPI readback speed		50	MHz
t_ES	Clock to enable low time	10		ns
t_CS	Clock to data wait time		10	ns
t_CWH	Clock pulse width high	10		ns
t_CWL	Clock pulse width low	10		ns
t_CES	Enable to clock setup time	10		ns
t_EWH	Enable pulse width high	10		ns

(1) See Figure 1

(2) See Figure 2

Figure 1. Serial Data Input Timing Diagram

There are several other considerations for writing on the SPI:

The R/W bit must be set to 0.
The signal on the SDI pin is clocked into a shift register on each rising edge of the SCK pin.
The CSB must be held low for data to be clocked. Device ignores clock pulses if CSB is held high.
The CSB transition from high to low must occur when SCK is low.
When SCK and SDI lines are shared between devices, TI recommends holding the CSB line high on any devices besides the intended programming target.

Figure 2. Serial Data Readback Timing Diagram

There are several other considerations for SPI readback:

The R/W bit must be set to 1.
The MUXOUT pin is always for the address portion of the transaction.
The address on the SDI pin is clocked into a shift register on each rising edge of the SCK pin.
The data portion of the transaction on the SDI line is always ignored.
The data on the MUXOUT pin should be considered valid on each rising edge of the SCK pin, provided all timing requirements are met.
All CSB considerations for SPI writing also apply to SPI readback.