ZHCSHW1C March   2018  – January 2019 ADS1260 , ADS1261

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      框图
  4. 4 修订历史记录
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Noise Performance
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Analog Inputs
        1. 9.3.1.1 ESD Diodes
        2. 9.3.1.2 Input Multiplexer
        3. 9.3.1.3 Temperature Sensor
        4. 9.3.1.4 Power-Supply Readback
        5. 9.3.1.5 Inputs Open
        6. 9.3.1.6 Internal VCOM Connection
        7. 9.3.1.7 Alternate Functions
      2. 9.3.2  PGA
        1. 9.3.2.1 PGA Bypass Mode
        2. 9.3.2.2 PGA Voltage Monitor
      3. 9.3.3  Reference Voltage
        1. 9.3.3.1 Internal Reference
        2. 9.3.3.2 External Reference
        3. 9.3.3.3 AVDD - AVSS Reference (Default)
        4. 9.3.3.4 Reference Monitor
      4. 9.3.4  Level-Shift Voltage (VBIAS)
      5. 9.3.5  Burn-Out Current Sources
      6. 9.3.6  Sensor-Excitation Current Sources (IDAC1 and IDAC2)
      7. 9.3.7  General-Purpose Input/Outputs (GPIOs)
      8. 9.3.8  Oversampling
      9. 9.3.9  Modulator
      10. 9.3.10 Digital Filter
        1. 9.3.10.1 Sinc Filter
          1. 9.3.10.1.1 Sinc Filter Frequency Response
        2. 9.3.10.2 FIR Filter
          1. 9.3.10.2.1 FIR Filter Frequency Response
        3. 9.3.10.3 Filter Bandwidth
        4. 9.3.10.4 50-Hz and 60-Hz Normal Mode Rejection
    4. 9.4 Device Functional Modes
      1. 9.4.1 Conversion Control
        1. 9.4.1.1 Continuous-Conversion Mode
        2. 9.4.1.2 Pulse-Conversion Mode
        3. 9.4.1.3 Conversion Latency
        4. 9.4.1.4 Start-Conversion Delay
      2. 9.4.2 Chop Mode
      3. 9.4.3 AC-Excitation Mode
      4. 9.4.4 ADC Clock Mode
      5. 9.4.5 Power-Down Mode
        1. 9.4.5.1 Hardware Power-Down
        2. 9.4.5.2 Software Power-Down
      6. 9.4.6 Reset
        1. 9.4.6.1 Power-on Reset
        2. 9.4.6.2 Reset by Pin
        3. 9.4.6.3 Reset by Command
      7. 9.4.7 Calibration
        1. 9.4.7.1 Offset and Full-Scale Calibration
          1. 9.4.7.1.1 Offset Calibration Registers
          2. 9.4.7.1.2 Full-Scale Calibration Registers
        2. 9.4.7.2 Offset Self-Calibration (SFOCAL)
        3. 9.4.7.3 Offset System-Calibration (SYOCAL)
        4. 9.4.7.4 Full-Scale Calibration (GANCAL)
        5. 9.4.7.5 Calibration Command Procedure
        6. 9.4.7.6 User Calibration Procedure
    5. 9.5 Programming
      1. 9.5.1 Serial Interface
        1. 9.5.1.1 Chip Select (CS)
        2. 9.5.1.2 Serial Clock (SCLK)
        3. 9.5.1.3 Data Input (DIN)
        4. 9.5.1.4 Data Output/Data Ready (DOUT/DRDY)
        5. 9.5.1.5 Serial Interface Auto-Reset
      2. 9.5.2 Data Ready (DRDY)
        1. 9.5.2.1 DRDY in Continuous-Conversion Mode
        2. 9.5.2.2 DRDY in Pulse-Conversion Mode
        3. 9.5.2.3 Data Ready by Software Polling
      3. 9.5.3 Conversion Data
        1. 9.5.3.1 Status byte (STATUS)
        2. 9.5.3.2 Conversion Data Format
      4. 9.5.4 CRC
      5. 9.5.5 Commands
        1. 9.5.5.1  NOP Command
        2. 9.5.5.2  RESET Command
        3. 9.5.5.3  START Command
        4. 9.5.5.4  STOP Command
        5. 9.5.5.5  RDATA Command
        6. 9.5.5.6  SYOCAL Command
        7. 9.5.5.7  GANCAL Command
        8. 9.5.5.8  SFOCAL Command
        9. 9.5.5.9  RREG Command
        10. 9.5.5.10 WREG Command
        11. 9.5.5.11 LOCK Command
        12. 9.5.5.12 UNLOCK Command
    6. 9.6 Register Map
      1. 9.6.1  Device Identification (ID) Register (address = 00h) [reset = xxh]
        1. Table 30. ID Register Field Descriptions
      2. 9.6.2  Device Status (STATUS) Register (address = 01h) [reset = 01h]
        1. Table 31. STATUS Register Field Descriptions
      3. 9.6.3  Mode 0 (MODE0) Register (address = 02h) [reset = 24h]
        1. Table 32. MODE0 Register Field Descriptions
      4. 9.6.4  Mode 1 (MODE1) Register (address = 03h) [reset = 01h]
        1. Table 33. MODE1 Register Field Descriptions
      5. 9.6.5  Mode 2 (MODE2) Register (address = 04h) [reset = 00h]
        1. Table 34. MODE2 Register Field Descriptions
      6. 9.6.6  Mode 3 (MODE3) Register (address = 05h) [reset = 00h]
        1. Table 35. MODE3 Register Field Descriptions
      7. 9.6.7  Reference Configuration (REF) Register (address = 06h) [reset = 05h]
        1. Table 36. REF Register Field Descriptions
      8. 9.6.8  Offset Calibration (OFCALx) Registers (address = 07h, 08h, 09h) [reset = 00h, 00h, 00h]
        1. Table 37. OFCAL0, OFCAL1, OFCAL2 Registers Field Description
      9. 9.6.9  Full-Scale Calibration (FSCALx) Registers (address = 0Ah, 0Bh, 0Ch) [reset = 00h, 00h, 40h]
        1. Table 38. FSCAL0, FSCAL1, FSCAL2 Registers Field Description
      10. 9.6.10 IDAC Multiplexer (IMUX) Register (address = 0Dh) [reset = FFh]
        1. Table 39. IMUX Register Field Descriptions
      11. 9.6.11 IDAC Magnitude (IMAG) Register (address = 0Eh) [reset = 00h]
        1. Table 40. IMAG Register Field Descriptions
      12. 9.6.12 Reserved (RESERVED) Register (address = 0Fh) [reset = 00h]
        1. Table 41. RESERVED Register Field Descriptions
      13. 9.6.13 PGA Configuration (PGA) Register (address = 10h) [reset = 00h]
        1. Table 42. PGA Register Field Descriptions
      14. 9.6.14 Input Multiplexer (INPMUX) Register (address = 11h) [reset = FFh]
        1. Table 43. INPMUX Register Field Descriptions
      15. 9.6.15 Input Bias (INPBIAS) Register (address = 12h) [reset = 00h]
        1. Table 44. INPBIAS Register Field Descriptions
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Input Range
      2. 10.1.2 Input Overload
      3. 10.1.3 Burn-Out Current Source
      4. 10.1.4 Unused Inputs and Outputs
      5. 10.1.5 AC-Excitation
      6. 10.1.6 Serial Interface and Digital Connections
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
    3. 10.3 Initialization Setup
  11. 11Power Supply Recommendations
    1. 11.1 Power-Supply Decoupling
    2. 11.2 Analog Power-Supply Clamp
    3. 11.3 Power-Supply Sequencing
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13器件和文档支持
    1. 13.1 文档支持
      1. 13.1.1 相关文档
    2. 13.2 相关链接
    3. 13.3 接收文档更新通知
    4. 13.4 社区资源
    5. 13.5 商标
    6. 13.6 静电放电警告
    7. 13.7 术语表
  14. 14机械、封装和可订购信息

7.5 Electrical Characteristics

minimum and maximum specifications apply from TA = –40°C to +125°C; typical specifications are at TA = 25°C; all specifications are at AVDD = 5 V, AVSS = 0 V, DVDD = 3.3 V, VREF = 2.5 V, fCLK = 7.3728 MHz, PGA mode, gain = 1, and data rate = 20 SPS (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUTS
Absolute input current PGA mode, V(AINx) = 2.5 V 4 6 nA
PGA bypass 200
Absolute input current drift 0.01 nA/°C
Differential input current PGA mode, VIN = 19 mV ±0.1 nA
PGA mode, VIN = 2.5 V –3 ±1 3
PGA mode, chop mode(5) ±5
PGA bypass, VIN = 2.5 V ±40
Differential input current drift 0.05 nA/°C
Differential input impedance PGA mode 1 GΩ
PGA bypass 50 MΩ
Crosstalk 0.1 µV/V
PGA
Gain settings 1, 2, 4, 8, 16, 32, 64, 128 V/V
Antialias filter frequency CCAPP, CAPN = 4.7 nF 60 kHz
PERFORMANCE
Resolution No missing codes 24 Bits
DR Data rate 2.5 40000 SPS
Noise performance See Table 1
INL Integral nonlinearity Gain = 1 to 16 –10 ±2 10 ppmFSR
Gain = 32 to 128 –12 ±3 12
Gain = 1 to 32 (40 kSPS) –15 ±5 15
VOS Offset voltage TA = 25°C –175 / gain – 5 ±50 / gain 175 / gain + 5 µV
TA = 25°C, chop mode –0.5 / gain – 0.05 ±0.2 / gain 0.5 / gain + 0.05
After calibration On the level of noise
Offset voltage drift Gain = 1 to 8 100 / gain 350 / gain nV/°C
Gain = 16 to 128 10 50
Chop mode, gain = 1 to 128 1 5
Offset voltage long-term drift Gain = 1, 1000 hr ±0.1 µV
GE Gain error TA = 25°C, gain = 1 to 128 –0.5% ±0.05% 0.5%
After calibration On the level of noise
Gain drift Gain = 1 to 128 0.5 4 ppm/°C
NMRR Normal-mode rejection ratio(1) See Table 7
CMRR Common-mode rejection ratio(2) Data rate = 20 SPS 130 dB
Data rate = 400 SPS 105 115
PSRR Power-supply rejection ratio(3) AVDD and AVSS 85 100 dB
DVDD 100 120
INTERNAL OSCILLATOR
fCLK Frequency 2.5 SPS to 25.6 kSPS 7.3728 MHz
40 kSPS 10.24
Accuracy –2% ±0.5% 2%
VOLTAGE REFERENCE INPUTS
Absolute input current ±250 nA
Input current vs voltage 15 nA/V
Input current drift 0.2 nA/°C
Input impedance Differential 30 MΩ
INTERNAL VOLTAGE REFERENCE(7)
Voltage 2.5 V
Initial error TA = 25°C, ADS1260B, ADS1261B ±0.1% ±0.2%
TA = 25°C, ADS1261 ±0.2%
Temperature drift TA = 0°C to +85°C, ADS1260B, ADS1261B 2 9 ppm/°C
TA = –40°C to +125°C, ADS1260B, ADS1261B 4 12
TA = –40°C to +125°C, ADS1261 10 40
Long-term drift 1000 hr ±25 ppm
Thermal hysteresis(8) First temperature cycle ±70 ppm
Second temperature cycle ±20
Output current –10 10 mA
Load regulation 50 µV/mA
Start-up time Settling time to ±0.001% of final value 100 ms
EXCITATION CURRENT SOURCES (IDACS)
Current settings 50, 100, 250, 500, 750,
1000, 1500, 2000, 2500, 3000		 µA
Compliance range AVSS AVDD – 1.1 V
Accuracy –4% ±0.7% 4%
Match error Same current magnitudes –1% ±0.1% 1%
Different current magnitudes ±1%
Temperature drift Absolute 50 ppm/°C
Match drift, IIDAC1 = IIDAC2 5 25
LEVEL-SHIFT VOLTAGE (VBIAS)
Voltage (AVDD + AVSS) / 2 V
Output impedance 100 Ω
BURN-OUT CURRENT SOURCES
Current settings Sink and source 0.05, 0.2, 1, 10 µA
Accuracy 0.05-µA range 0.025 0.05 0.075 µA
TEMPERATURE SENSOR
Sensor voltage TA = 25°C 122.4 mV
Temperature coefficient 420 µV/°C
MONITORS
PGA output Low AVSS + 0.2 V
High AVDD – 0.2
Reference voltage Low 0.4 0.6 V
GENERAL-PURPOSE INPUTS/OUTPUTS (GPIOs)(6)
VOL Low-level output voltage IOL = –1 mA 0.2 · AVDD V
VOH High-level output voltage IOH = 1 mA 0.8 · AVDD V
VIL Low-level input voltage 0.3 · AVDD V
VIH High-level input voltage 0.7 · AVDD V
Input hysteresis 0.5 V
DIGITAL INPUTS/OUTPUTS (Other Than GPIOs)
VOL Low-level output voltage IOL = –1 mA 0.2 · DVDD V
IOL = –8 mA 0.2 · DVDD
VOH High-level output voltage IOH = 1 mA 0.8 · DVDD V
IOH = 8 mA 0.75 · DVDD
VIL Low-level input voltage 0.3 · DVDD V
VIH High-level input voltage 0.7 · DVDD V
Input hysteresis 0.1 V
Input leakage VIH or VIL –10 10 µA
POWER SUPPLY
IAVDD,
IAVSS 		Analog supply current PGA bypass 2.7 4.5 mA
PGA mode, gain = 1 to 32 3.8 6
PGA mode, gain = 64 or 128 4.3 6.5
Power-down mode 2 8 µA
IAVDD,
IAVSS 		Analog supply current (by function) Voltage reference 0.2 mA
40-kSPS mode 0.5
Current sources As programmed
IDVDD Digital supply current 20 SPS 0.4 0.65 mA
40 kSPS 0.6 0.85
Power-down mode(4) 30 50 µA
PD Power dissipation PGA mode 20 32 mW
Power-down mode 0.1 0.2
(1) Normal-mode rejection ratio performance depends on the digital filter configuration.
(2) Common-mode rejection ratio is specified at 60 Hz.
(3) Power-supply rejection ratio specified at dc. PSRR (dB) = 20 Log (Δ power supply voltage / Δ offset voltage).
(4) CLKIN input stopped.
(5) Chop-mode input current scales with data rate.
(6) GPIO voltage with respect to AVSS.
(7) Soldered to PCB using recommended PCB layout pattern and using reflow profile per JEDEC standard J-STD-020D.1
(8) Voltage reference hysteresis measured by operating the device at 25°C cycling the device to 0°C and 105°C and returning the device to 25°C.
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