ZHCSHW1C March   2018  – January 2019 ADS1260 , ADS1261

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      框图
  4. 4 修订历史记录
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Noise Performance
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Analog Inputs
        1. 9.3.1.1 ESD Diodes
        2. 9.3.1.2 Input Multiplexer
        3. 9.3.1.3 Temperature Sensor
        4. 9.3.1.4 Power-Supply Readback
        5. 9.3.1.5 Inputs Open
        6. 9.3.1.6 Internal VCOM Connection
        7. 9.3.1.7 Alternate Functions
      2. 9.3.2  PGA
        1. 9.3.2.1 PGA Bypass Mode
        2. 9.3.2.2 PGA Voltage Monitor
      3. 9.3.3  Reference Voltage
        1. 9.3.3.1 Internal Reference
        2. 9.3.3.2 External Reference
        3. 9.3.3.3 AVDD - AVSS Reference (Default)
        4. 9.3.3.4 Reference Monitor
      4. 9.3.4  Level-Shift Voltage (VBIAS)
      5. 9.3.5  Burn-Out Current Sources
      6. 9.3.6  Sensor-Excitation Current Sources (IDAC1 and IDAC2)
      7. 9.3.7  General-Purpose Input/Outputs (GPIOs)
      8. 9.3.8  Oversampling
      9. 9.3.9  Modulator
      10. 9.3.10 Digital Filter
        1. 9.3.10.1 Sinc Filter
          1. 9.3.10.1.1 Sinc Filter Frequency Response
        2. 9.3.10.2 FIR Filter
          1. 9.3.10.2.1 FIR Filter Frequency Response
        3. 9.3.10.3 Filter Bandwidth
        4. 9.3.10.4 50-Hz and 60-Hz Normal Mode Rejection
    4. 9.4 Device Functional Modes
      1. 9.4.1 Conversion Control
        1. 9.4.1.1 Continuous-Conversion Mode
        2. 9.4.1.2 Pulse-Conversion Mode
        3. 9.4.1.3 Conversion Latency
        4. 9.4.1.4 Start-Conversion Delay
      2. 9.4.2 Chop Mode
      3. 9.4.3 AC-Excitation Mode
      4. 9.4.4 ADC Clock Mode
      5. 9.4.5 Power-Down Mode
        1. 9.4.5.1 Hardware Power-Down
        2. 9.4.5.2 Software Power-Down
      6. 9.4.6 Reset
        1. 9.4.6.1 Power-on Reset
        2. 9.4.6.2 Reset by Pin
        3. 9.4.6.3 Reset by Command
      7. 9.4.7 Calibration
        1. 9.4.7.1 Offset and Full-Scale Calibration
          1. 9.4.7.1.1 Offset Calibration Registers
          2. 9.4.7.1.2 Full-Scale Calibration Registers
        2. 9.4.7.2 Offset Self-Calibration (SFOCAL)
        3. 9.4.7.3 Offset System-Calibration (SYOCAL)
        4. 9.4.7.4 Full-Scale Calibration (GANCAL)
        5. 9.4.7.5 Calibration Command Procedure
        6. 9.4.7.6 User Calibration Procedure
    5. 9.5 Programming
      1. 9.5.1 Serial Interface
        1. 9.5.1.1 Chip Select (CS)
        2. 9.5.1.2 Serial Clock (SCLK)
        3. 9.5.1.3 Data Input (DIN)
        4. 9.5.1.4 Data Output/Data Ready (DOUT/DRDY)
        5. 9.5.1.5 Serial Interface Auto-Reset
      2. 9.5.2 Data Ready (DRDY)
        1. 9.5.2.1 DRDY in Continuous-Conversion Mode
        2. 9.5.2.2 DRDY in Pulse-Conversion Mode
        3. 9.5.2.3 Data Ready by Software Polling
      3. 9.5.3 Conversion Data
        1. 9.5.3.1 Status byte (STATUS)
        2. 9.5.3.2 Conversion Data Format
      4. 9.5.4 CRC
      5. 9.5.5 Commands
        1. 9.5.5.1  NOP Command
        2. 9.5.5.2  RESET Command
        3. 9.5.5.3  START Command
        4. 9.5.5.4  STOP Command
        5. 9.5.5.5  RDATA Command
        6. 9.5.5.6  SYOCAL Command
        7. 9.5.5.7  GANCAL Command
        8. 9.5.5.8  SFOCAL Command
        9. 9.5.5.9  RREG Command
        10. 9.5.5.10 WREG Command
        11. 9.5.5.11 LOCK Command
        12. 9.5.5.12 UNLOCK Command
    6. 9.6 Register Map
      1. 9.6.1  Device Identification (ID) Register (address = 00h) [reset = xxh]
        1. Table 30. ID Register Field Descriptions
      2. 9.6.2  Device Status (STATUS) Register (address = 01h) [reset = 01h]
        1. Table 31. STATUS Register Field Descriptions
      3. 9.6.3  Mode 0 (MODE0) Register (address = 02h) [reset = 24h]
        1. Table 32. MODE0 Register Field Descriptions
      4. 9.6.4  Mode 1 (MODE1) Register (address = 03h) [reset = 01h]
        1. Table 33. MODE1 Register Field Descriptions
      5. 9.6.5  Mode 2 (MODE2) Register (address = 04h) [reset = 00h]
        1. Table 34. MODE2 Register Field Descriptions
      6. 9.6.6  Mode 3 (MODE3) Register (address = 05h) [reset = 00h]
        1. Table 35. MODE3 Register Field Descriptions
      7. 9.6.7  Reference Configuration (REF) Register (address = 06h) [reset = 05h]
        1. Table 36. REF Register Field Descriptions
      8. 9.6.8  Offset Calibration (OFCALx) Registers (address = 07h, 08h, 09h) [reset = 00h, 00h, 00h]
        1. Table 37. OFCAL0, OFCAL1, OFCAL2 Registers Field Description
      9. 9.6.9  Full-Scale Calibration (FSCALx) Registers (address = 0Ah, 0Bh, 0Ch) [reset = 00h, 00h, 40h]
        1. Table 38. FSCAL0, FSCAL1, FSCAL2 Registers Field Description
      10. 9.6.10 IDAC Multiplexer (IMUX) Register (address = 0Dh) [reset = FFh]
        1. Table 39. IMUX Register Field Descriptions
      11. 9.6.11 IDAC Magnitude (IMAG) Register (address = 0Eh) [reset = 00h]
        1. Table 40. IMAG Register Field Descriptions
      12. 9.6.12 Reserved (RESERVED) Register (address = 0Fh) [reset = 00h]
        1. Table 41. RESERVED Register Field Descriptions
      13. 9.6.13 PGA Configuration (PGA) Register (address = 10h) [reset = 00h]
        1. Table 42. PGA Register Field Descriptions
      14. 9.6.14 Input Multiplexer (INPMUX) Register (address = 11h) [reset = FFh]
        1. Table 43. INPMUX Register Field Descriptions
      15. 9.6.15 Input Bias (INPBIAS) Register (address = 12h) [reset = 00h]
        1. Table 44. INPBIAS Register Field Descriptions
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Input Range
      2. 10.1.2 Input Overload
      3. 10.1.3 Burn-Out Current Source
      4. 10.1.4 Unused Inputs and Outputs
      5. 10.1.5 AC-Excitation
      6. 10.1.6 Serial Interface and Digital Connections
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
    3. 10.3 Initialization Setup
  11. 11Power Supply Recommendations
    1. 11.1 Power-Supply Decoupling
    2. 11.2 Analog Power-Supply Clamp
    3. 11.3 Power-Supply Sequencing
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13器件和文档支持
    1. 13.1 文档支持
      1. 13.1.1 相关文档
    2. 13.2 相关链接
    3. 13.3 接收文档更新通知
    4. 13.4 社区资源
    5. 13.5 商标
    6. 13.6 静电放电警告
    7. 13.7 术语表
  14. 14机械、封装和可订购信息

7.8 Typical Characteristics

at TA = 25°C, AVDD = 5 V, AVSS = 0 V, DVDD = 3.3 V, VREF = 2.5 V, data rate = 20 SPS, fCLK = 7.3728 MHz (fCLK = 10.24 MHz for data rate = 40 kSPS), and gain = 1 (unless otherwise noted)
ADS1260 ADS1261 D009_SBAS760.gif
After calibration, shorted input
Figure 9. Offset Voltage vs Temperature
ADS1260 ADS1261 D012_SBAS760.gif
Shorted input, 30 units
Figure 11. Offset Voltage Drift Distribution
ADS1260 ADS1261 D001_SBAS760.gif
After calibration
Figure 13. Offset Voltage vs Reference Voltage
ADS1260 ADS1261 D014_SBAS760.gif
After calibration
Figure 15. Gain Error vs Temperature
ADS1260 ADS1261 D002_SBAS760.gif
After calibration
Figure 17. Gain Error vs Reference Voltage
ADS1260 ADS1261 D004_SBAS760.gif
7200 SPS, Sinc1
Figure 19. Noise vs Temperature
ADS1260 ADS1261 D006_SBAS760.gif
Figure 21. Noise vs Reference Voltage
ADS1260 ADS1261 D029_SBAS760.gif
20 SPS, gain = 128, 256 data points
Figure 23. Conversion Data Histogram
ADS1260 ADS1261 D031_SBAS760.gif
7200 SPS, gain = 128, 8192 data points
Figure 25. Conversion Data Histogram
ADS1260 ADS1261 D007_SBAS760.gif
Figure 27. Integral Nonlinearity vs Temperature
ADS1260 ADS1261 D008_SBAS760.gif
Figure 29. Integral Nonlinearity vs Reference Voltage
ADS1260 ADS1261 D204_SBAS760.gif
After calibration, 30 units
Figure 31. Voltage Reference Long-Term Drift
ADS1260 ADS1261 D017_SBAS760.gif
30 units
Figure 33. Temperature Sensor Voltage Histogram
ADS1260 ADS1261 D018_SBAS760.gif
Figure 35. Operating Current vs Temperature
ADS1260 ADS1261 D026_SBAS760.gif
Figure 37. PGA Low Monitor Threshold
ADS1260 ADS1261 D150_SBAS760.gif
Data rate = 1200 SPS
Figure 39. CMRR vs Frequency
ADS1260 ADS1261 D034_SBAS760.gif
Figure 41. CMRR and PSRR vs Temperature
ADS1260 ADS1261 D019_SBAS760.gif
IIDAC = 250 µA
Figure 43. IDAC Current vs IDAC Voltage
ADS1260 ADS1261 D021_SBAS760.gif
IIDAC = 3000 µA
Figure 45. IDAC Current vs IDAC Voltage
ADS1260 ADS1261 D035_SBAS760.gif
IIDAC1 = IIDAC2 = 1000 µA
Figure 47. IDAC Current Match vs IDAC Voltage
ADS1260 ADS1261 D010_SBAS760.gif
Chop mode, after calibration, shorted input
Figure 10. Offset Voltage vs Temperature
ADS1260 ADS1261 D011_SBAS760.gif
Chop mode, shorted input, 30 units
Figure 12. Offset Voltage Drift Distribution
ADS1260 ADS1261 D205_SBAS760.gif
After calibration, gain = 1
Figure 14. Offset Voltage Long-Term Drift
ADS1260 ADS1261 D013_SBAS760.gif
30 units
Figure 16. Gain Error Drift Distributions
ADS1260 ADS1261 D003_SBAS760.gif
20 SPS, Sinc4
Figure 18. Noise vs Temperature
ADS1260 ADS1261 D005_SBAS760.gif
40000 SPS, Sinc5
Figure 20. Noise vs Temperature
ADS1260 ADS1261 D028_SBAS760.gif
20 SPS, gain = 4, 256 data points
Figure 22. Conversion Data Histogram
ADS1260 ADS1261 D030_SBAS760.gif
7200 SPS, gain = 4, 8192 data points
Figure 24. Conversion Data Histogram
ADS1260 ADS1261 D033_SBAS760.gif
Figure 26. Integral Nonlinearity vs VIN
ADS1260 ADS1261 D015_SBAS760.gif
30 Units
Figure 28. Integral Nonlinearity Distribution
ADS1260 ADS1261 D102_SBAS760.gif
ADS1260B, ADS1261B - 30 units
Figure 30. Voltage Reference vs Temperature
ADS1260 ADS1261 D024_SBAS760.gif
IREFP measured with VREFN = AVSS
IREFN measured with VREFP = AVDD
Figure 32. Reference Input Current vs Reference Voltage
ADS1260 ADS1261 D016_SBAS760.gif
30 units
Figure 34. Internal Oscillator vs Temperature
ADS1260 ADS1261 D025_SBAS760.gif
Figure 36. PGA High Monitor Threshold
ADS1260 ADS1261 D027_SBAS760.gif
Figure 38. Reference Voltage Low Alarm Threshold
ADS1260 ADS1261 D151_SBAS760.gif
Data rate = 1200 SPS
Figure 40. PSRR vs Frequency
ADS1260 ADS1261 D022_SBAS760.gif
IIDAC = 50 µA
Figure 42. IDAC Current vs IDAC Voltage
ADS1260 ADS1261 D020_SBAS760.gif
IIDAC = 1000 µA
Figure 44. IDAC Current vs IDAC Voltage
ADS1260 ADS1261 D023_SBAS760.gif
IIDAC1 = IIDAC2 = 250 µA
Figure 46. IDAC Current Match vs IDAC Voltage
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