ZHCSHY7A April 2018 – May 2018 UCC28742
PRODUCTION DATA.
There is comprehensive fault protection incorporated into the UCC28742. Protection functions include:
Output Over-Voltage: The output over-voltage function is determined by the voltage feedback on the VS pin. If the voltage sample on VS exceeds 4.65 V (VOVP), for three consecutive switching cycles an OV fault is asserted. Once asserted the device stops switching, initiating a UVLO reset and re-start fault cycle. During the fault, the VDD bias current remains at the run current level, discharging the VDD pin to the UVLO turn-off threshold, VVDD(off). After that, the device returns to the start state, VDD now charging to VVDD(on) where switching is initiated. The UVLO sequence repeats as long as the fault condition persists.
Input Under-Voltage: The line input run and stop thresholds are determined by current information at the VS pin during the MOSFET on-time. While the VS pin is clamped close to GND during the MOSFET on-time, the current through RS1, out of the VS pin, is monitored to determine a sample of the bulk capacitor voltage. A wide separation of run and stop thresholds allows clean start-up and shut-down of the power supply with the line voltage. From the start state, the sensed VS current, IVSL, must exceed the run current threshold, IVSL(run) (typical 211 µA), within the first three cycles after switching starts as VDD reaches VVDD(on). If it does not, then switching stops and the UVLO reset and re-start fault cycle is initiated. Once running, IVSL must drop below the stop level, IVSL(stop) (typically 75 µA), for three consecutive cycles to initiate the fault response.
Primary Over-Current: The UCC28742 always operates with cycle-by-cycle primary-peak current control. The normal operating range of the CS pin is 190 mV to 770 mV. If the voltage on CS exceeds the 1.5-V over-current level, any time after the internal leading edge blanking time and before the end of the transformer demagnetization, for three consecutive cycles, the device shuts down and the UVLO reset and re-start fault cycle begins.
CS Pin Open: The CS pin has a 2-µA minimum pull-up that brings the CS pin above the 1.5-V OC fault level if the CS pin is open. This causes the primary over-current fault after three cycles.
CS Pin Short to GND: On the first, and only the first, cycle at start-up during power on, the device checks to verify that the VCST(min) threshold is reached at the CS pin within 5 µs of DRV going high. If the CS voltage fails to reach this level then the device terminates the current cycle and immediately enters the UVLO reset and re-start fault sequence.
VS Pin: Protection is included in the event of component failures on the VS pin. If the high-side VS divider resistor opens the controller stops switching. VDD collapses to its VVDD(off) threshold, a start-up attempt follows with a single DRV on-time when VDD reaches VVDD(on). The UVLO cycle will repeat. If the low-side VS divider resistor is open then an output over-voltage fault occurs.
Device Internal OTP: The internal over-temperature protection threshold is 165 °C. If the junction temperature of the device reaches this threshold the device initiates the UVLO reset and re-start fault cycle. If the temperature is still high at the end of the UVLO cycle, the protection cycle repeats.
Constant Current Limit and Delayed Output Shutdown - Output Over-Current Protection: The load over-current protection is made precisely using constant current limit and delayed output shutdown as described in section Constant Current Limit and Delayed Shutdown