ZHCSI01C April   2018  – October 2019 LMR36006

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      简化原理图
  4. 4 修订历史记录
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 System Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power-Good Flag Output
      2. 8.3.2 Enable and Start-up
      3. 8.3.3 Current Limit and Short Circuit
      4. 8.3.4 Undervoltage Lockout and Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Auto Mode
      2. 8.4.2 Dropout
      3. 8.4.3 Minimum Switch On-Time
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design 1: Low Power 24-V, 600-mA PFM Converter
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1  Custom Design With WEBENCH Tools
          2. 9.2.1.2.2  Choosing the Switching Frequency
          3. 9.2.1.2.3  Setting the Output Voltage
          4. 9.2.1.2.4  Inductor Selection
          5. 9.2.1.2.5  Output Capacitor Selection
          6. 9.2.1.2.6  Input Capacitor Selection
          7. 9.2.1.2.7  CBOOT
          8. 9.2.1.2.8  VCC
          9. 9.2.1.2.9  CFF Selection
            1. 9.2.1.2.9.1 External UVLO
          10. 9.2.1.2.10 Maximum Ambient Temperature
      2. 9.2.2 Application Curves
      3. 9.2.3 Design 2: High Density 24-V, 600-mA PFM Converter
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Application Curves
    3. 9.3 What to Do and What Not to Do
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Ground and Thermal Considerations
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 器件支持
      1. 12.1.1 开发支持
        1. 12.1.1.1 使用 WEBENCH® 工具创建定制设计方案
    2. 12.2 文档支持
      1. 12.2.1 相关文档
    3. 12.3 接收文档更新通知
    4. 12.4 支持资源
    5. 12.5 商标
    6. 12.6 静电放电警告
    7. 12.7 Glossary
  13. 13机械、封装和可订购信息

7.5 Electrical Characteristics

Limits apply over operating junction temperature (TJ ) range of –40°C to +150°C, unless otherwise stated. Minimum and Maximum limits(1) are specified through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions apply: VIN = 24 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE (VIN PIN)
IQ-nonSW Operating quiescent current (non-switching)(2) VEN = 3.3 V (PFM variant only) 18 26 36 µA
ISD Shutdown quiescent current; measured at VIN pin VEN = 0 V 5 µA
ENABLE (EN PIN)
VEN-VCC-H Enable input high level for VCC output VENABLE rising 1.14 V
VEN-VCC-L Enable input low level for VCC output VENABLE falling 0.3 V
VEN-VOUT-H Enable input high level for VOUT VENABLE rising 1.157 1.231 1.3 V
VEN-VOUT-HYS Enable input hysteresis for VOUT Hysteresis below VENABLE-H; falling 110 mV
ILKG-EN Enable input leakage current VEN = 3.3V 0.2 nA
INTERNAL LDO (VCC PIN)
VCC Internal VCC voltage 6 V ≤ VIN ≤ 60 V 4.75 5 5.25 V
VCC-UVLO-Rising Internal VCC undervoltage lockout VCC rising 3.6 3.8 4.0 V
VCC-UVLO-Falling Internal VCC undervoltage lockout VCC falling 3.1 3.3 3.5 V
VOLTAGE REFERENCE (FB PIN)
VFB Feedback voltage 0.985 1 1.015 V
ILKG-FB Feedback leakage current FB = 1 V 0.2 nA
CURRENT LIMITS AND HICCUP
ISC High-side current limit(3) 0.8 1 1.2 A
ILS-LIMIT Low-side current limit(3) 0.6 0.8 0.95 A
IL-ZC Zero cross detector threshold PFM variants only 0.02 A
IPEAK-MIN Minimum inductor peak current(3) 0.18 A
POWER GOOD (PGOOD PIN)
VPG-HIGH-UP Power-Good upper threshold - rising % of FB voltage 105% 107% 110%
VPG-LOW-DN Power-Good lower threshold - falling % of FB voltage 90% 93% 95%
VPG-HYS Power-Good hysteresis (rising & falling) % of FB voltage 2%
TPG Power-Good rising/falling edge deglitch delay 80 140 200 µs
VPG-VALID Minimum input voltage for proper Power-Good function 2 V
RPG Power-Good on-resistance VEN = 2.5 V 80 165 Ω
RPG Power-Good on-resistance VEN = 0 V 35 90 Ω
OSCILLATOR
FOSC Internal oscillator frequency 2.1-MHz variant 1.95 2.1 2.35 MHz
FOSC Internal oscillator frequency 1-MHz variant 0.85 1 1.15 MHz
MOSFETS
RDS-ON-HS High-side MOSFET ON-resistance IOUT = 0.5 A 225 435 mΩ
RDS-ON-LS Low-side MOSFET ON-resistance IOUT = 0.5 A 150 280 mΩ
(1) MIN and MAX limits are 100% production tested at 25℃. Limits over the operating temperature range verified through correlation using
Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
(2) This is the current used by the device open loop. It does not represent the total input current of the system when in regulation.
(3) The current limit values in this table are tested, open loop, in production. They may differ from those found in a closed loop application.
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