ZHCSI04E September 2009 – April 2018 TPS54418
PRODUCTION DATA.
- 1 特性
- 2 应用
- 3 说明
- 4 修订历史记录
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Fixed Frequency PWM Control
- 7.3.2 Slope Compensation and Output Current
- 7.3.3 Bootstrap Voltage (Boot) and Low Dropout Operation
- 7.3.4 Error Amplifier
- 7.3.5 Voltage Reference
- 7.3.6 Adjusting the Output Voltage
- 7.3.7 Enable and Adjusting Undervoltage Lockout
- 7.3.8 Soft-Start Pin
- 7.3.9 Sequencing
- 7.3.10 Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
- 7.3.11 Overcurrent Protection
- 7.3.12 Frequency Shift
- 7.3.13 Reverse Overcurrent Protection
- 7.3.14 Synchronize Using the RT/CLK Pin
- 7.3.15 Power Good (PWRGD Pin)
- 7.3.16 Overvoltage Transient Protection
- 7.3.17 Thermal Shutdown
- 7.4 Device Functional Modes
-
8 Application and Implementation
- 8.1 Application Information
- 8.2
Typical Application
- 8.2.1 Design Requirements
- 8.2.2
Detailed Design Procedure
- 8.2.2.1 Step One: Select the Switching Frequency
- 8.2.2.2 Step Two: Select the Output Inductor
- 8.2.2.3 Step Three: Choose the Output Capacitor
- 8.2.2.4 Step Four: Select the Input Capacitor
- 8.2.2.5 Step Five: Minimum Load DC COMP Voltage
- 8.2.2.6 Step Six: Choose the Soft-Start Capacitor
- 8.2.2.7 Step Seven: Select the Bootstrap Capacitor
- 8.2.2.8 Step Eight: Undervoltage Lockout Threshold
- 8.2.2.9 Step Nine: Select Output Voltage and Feedback Resistors
- 8.2.2.10 Step 10: Select Loop Compensation Components
- 8.2.2.11 Power Dissipation Estimate
- 8.2.3 Application Curves
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文档支持
- 12机械、封装和可订购信息
8.2.2.10 Step 10: Select Loop Compensation Components
There are several industry techniques used to compensate DC/DC regulators. The method presented here is easy to calculate and yields high phase margins. For most conditions, the regulator has a phase margin between 60 and 90 degrees. The method presented here ignores the effects of the slope compensation that is internal to the TPS54418. Because the slope compensation is ignored, the actual crossover frequency is usually lower than the crossover frequency used in the calculations. Use SwitcherPro software for a more accurate design.
To get started, the modulator pole, fP(mod), and the esr zero, fZ1 must be calculated using Equation 37 and Equation 38. For COUT, derating the capacitor is not needed as the 1.8 V output is a small percentage of the 10 V capacitor rating. If the output is a high percentage of the capacitor rating, use the capacitor manufacturer information to derate the capacitor value. Use Equation 39 and Equation 40 to estimate a starting point for the crossover frequency, fC. For the example design, fP(mod) is 8.04 kHz and fZ1 is 2412 kHz. Equation 39 is the geometric mean of the modulator pole and the esr zero and Equation 40 is the mean of modulator pole and the switching frequency. Equation 39 yields 139 kHz and Equation 40 gives 63 kHz. Use the lower value of Equation 39 or Equation 40 as the maximum crossover frequency. For this example, fc is 35 kHz. Next, the compensation components are calculated. A resistor in series with a capacitor is used to create a compensating zero. A capacitor in parallel to these two components forms the compensating pole (if needed).
The compensation design takes the following steps:
- Set up the anticipated cross-over frequency. Use Equation 41 to calculate the compensation network’s resistor value. In this example, the anticipated cross-over frequency fC is 35 kHz. The power stage gain (gM(ps)) is 13 A/V and the error amplifier gain (gM(ea)) is 225uA/V.
- Place compensation zero at the pole formed by the load resistor and the output capacitor. The compensation network’s capacitor can be calculated from Equation 42.
- An additional pole can be added to attenuate high frequency noise. In this application, it is not necessary to add it.
From the procedures above, start with a 11.2 kΩ resistor and a 2650pF capacitor. After prototyping and bode plot measurement, the optimized compensation network selected for this design includes a 7.5 kΩ resistor and a 2700 pF capacitor.