7.3.6 Soft-Start (Buck Controllers)

The buck controllers each have independent soft-start capability to limit inrush during start-up and to meet timing requirements of the Xilinx Spartan-3 FPGA. Limiting inrush current by using soft-start, or by staggering the turnon of power rails, also guards against voltage drops at the input source due to its output impedance. Refer to the soft-start circuitry shown in Figure 16 and the soft-start timing diagram shown in Figure 17. The BUCK1 controller is discussed in this section; it is identical to BUCK2. Note that pins SS1 and SS2 are very high-impedance and cannot be probed using a typical oscilloscope setup. When input voltage is applied at IN1 and EN1 is driven low, any charge on the SS pin is discharged by an on-chip pulldown transistor. When EN1 is driven high, an on-chip current source starts charging the external soft-start capacitor C_SS1. The voltage on the capacitor is compared to the voltage across the current sense resistor R1 to determine if an overcurrent condition exists. If the voltage drop across the sense resistor becomes greater than the reference voltage, then the external PMOS is shut off for the minimum off-time. This implementation provides a cycle-by-cycle current limit and lets the user configure the soft-start time over a wide range for most applications. For detailed information on selecting C_SS1 and C_SS2, see the Soft-Start Capacitor Selection (Buck Controllers) section.

Figure 16. Soft-Start Circuitry

Figure 17. Soft-Start Timing Diagram