8.2.2.3 External PMOS Transistor Selection (Buck Controllers)

The external PMOS transistor is selected based on threshold voltage (V_T), on-resistance (R_DS,ON), gate capacitance (C_G) and voltage rating. The PMOS V_T magnitude must be much lower than the lowest voltage at IN1 or IN2 that will be used. A V_T magnitude that is 0.5V less than the lowest input voltage is normally sufficient. The PMOS gate will see voltages from 0V to the maximum input voltage, so gate-to-source breakdown should be a few volts higher than the maximum input supply. The drain-to-source of the device will also see this full voltage swing, and should therefore be a few volts higher than the maximum input supply. The RMS current in the PMOS can be estimated by using Equation 9:

Equation 9.

The power dissipated in the PMOS is comprised of both conduction and switching losses. Switching losses are typically insignificant. The conduction losses are a function of the RMS current and the R_DS,ON of the PMOS, and are calculated by Equation 10:

Equation 10.