ZHCSI15L June 2006 – May 2018 TPS65023 , TPS65023B
PRODUCTION DATA.
This is the input to a capacitor that defines the reset delay time after the voltage at VRTC rises above 2.52 V. The timing is generated by charging and discharging the capacitor with a current of 2 μA between a threshold of 0.25 V and 1 V for 128 cycles. A 1-nF capacitor gives a delay time of 100 ms.
While there is no real upper and lower limit for the capacitor connected to TRESPWRON, TI recommends not leaving signal pins open.
where
The minimum and maximum values for the timing parameters called ICONST (2 uA), TRESPWRON_UPTH (1 V), and TRESPWRON_LOWTH (0.25 V) can be found under Electrical Characteristics.