ZHCSI67D May   2018  – December 2019 MSP430FR2153 , MSP430FR2155 , MSP430FR2353 , MSP430FR2355

PRODUCTION DATA.  

  1. 1器件概述
    1. 1.1 特性
    2. 1.2 应用
    3. 1.3 说明
    4. 1.4 功能方框图
      1.      修订历史记录
  2. 2Device Comparison
    1. 2.1 Related Products
  3. 3Terminal Configuration and Functions
    1. 3.1 Pin Diagrams
    2. 3.2 Pin Attributes
    3. 3.3 Signal Descriptions
    4. 3.4 Pin Multiplexing
    5. 3.5 Buffer Type
    6. 3.6 Connection of Unused Pins
  4. 4Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings
    3. 4.3  Recommended Operating Conditions
    4. 4.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 4.5  Active Mode Supply Current Per MHz
    6. 4.6  Low-Power Mode LPM0 Supply Currents Into VCC Excluding External Current
    7. 4.7  Low-Power Mode LPM3 and LPM4 Supply Currents (Into VCC) Excluding External Current
    8. 4.8  Low-Power Mode LPMx.5 Supply Currents (Into VCC) Excluding External Current
    9. 4.9  Production Distribution of LPM Supply Currents
    10. 4.10 Typical Characteristics - Current Consumption Per Module
    11. 4.11 Thermal Resistance Characteristics
    12. 4.12 Timing and Switching Characteristics
      1. 4.12.1  Power Supply Sequencing
        1. Table 4-1 PMM, SVS and BOR
      2. 4.12.2  Reset Timing
        1. Table 4-2 Wake-up Times From Low-Power Modes and Reset
      3. 4.12.3  Clock Specifications
        1. Table 4-3 XT1 Crystal Oscillator (Low Frequency)
        2. Table 4-4 XT1 Crystal Oscillator (High Frequency)
        3. Table 4-5 DCO FLL, Frequency
        4. Table 4-6 DCO Frequency
        5. Table 4-7 REFO
        6. Table 4-8 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        7. Table 4-9 Module Oscillator (MODOSC)
      4. 4.12.4  Internal Shared Reference
        1. Table 4-10 Internal Shared Reference
      5. 4.12.5  General-Purpose I/Os
        1. Table 4-11 Digital Inputs
        2. Table 4-12 Digital Outputs
      6. 4.12.6  Digital I/O Typical Characteristics
      7. 4.12.7  Timer_B
        1. Table 4-13 Timer_B
      8. 4.12.8  eUSCI
        1. Table 4-14 eUSCI (UART Mode) Clock Frequencies
        2. Table 4-15 eUSCI (UART Mode) Switching Characteristics
        3. Table 4-16 eUSCI (SPI Master Mode) Clock Frequency
        4. Table 4-17 eUSCI (SPI Master Mode) Switching Characteristics
        5. Table 4-18 eUSCI (SPI Slave Mode) Switching Characteristics
        6. Table 4-19 eUSCI (I2C Mode) Switching Characteristics
      9. 4.12.9  ADC
        1. Table 4-20 ADC, Power Supply and Input Range Conditions
        2. Table 4-21 ADC, Timing Parameters
        3. Table 4-22 ADC, Linearity Parameters
      10. 4.12.10 Enhanced Comparator (eCOMP)
        1. Table 4-23 eCOMP0
        2. Table 4-24 eCOMP1
      11. 4.12.11 Smart Analog Combo (SAC) (MSP430FR235x Devices Only)
        1. Table 4-25 SAC, OA
        2. Table 4-26 SAC, DAC
      12. 4.12.12 FRAM
        1. Table 4-27 FRAM
      13. 4.12.13 Emulation and Debug
        1. Table 4-28 JTAG, Spy-Bi-Wire Interface
        2. Table 4-29 JTAG, 4-Wire Interface
  5. 5Detailed Description
    1. 5.1  CPU
    2. 5.2  Operating Modes
    3. 5.3  Interrupt Vector Addresses
    4. 5.4  Memory Organization
    5. 5.5  Bootloader (BSL)
    6. 5.6  JTAG Standard Interface
    7. 5.7  Spy-Bi-Wire Interface (SBW)
    8. 5.8  FRAM
    9. 5.9  Memory Protection
    10. 5.10 Peripherals
      1. 5.10.1  Power Management Module (PMM) and On-Chip Reference Voltages
      2. 5.10.2  Clock System (CS) and Clock Distribution
      3. 5.10.3  General-Purpose Input/Output Port (I/O)
      4. 5.10.4  Watchdog Timer (WDT)
      5. 5.10.5  System Module (SYS)
      6. 5.10.6  Cyclic Redundancy Check (CRC)
      7. 5.10.7  Interrupt Compare Controller (ICC)
      8. 5.10.8  Enhanced Universal Serial Communication Interface (eUSCI_A0, eUSCI_A1, eUSCI_B0, eUSCI_B1)
      9. 5.10.9  Timers (Timer0_B3, Timer1_B3, Timer2_B3, Timer3_B7)
      10. 5.10.10 Backup Memory (BKMEM)
      11. 5.10.11 Real-Time Clock (RTC) Counter
      12. 5.10.12 12-Bit Analog-to-Digital Converter (ADC)
      13. 5.10.13 Enhanced Comparator
      14. 5.10.14 Manchester Function Module (MFM)
      15. 5.10.15 Smart Analog Combo (SAC) (MSP430FR235x Devices Only)
      16. 5.10.16 eCOMP0, eCOMP1, SAC0, SAC1, SAC2, and SAC3 Interconnection (MSP430FR235x Devices Only)
      17. 5.10.17 Cross-Chip Interconnection (SACx are MSP430FR235x Devices Only)
      18. 5.10.18 Embedded Emulation Module (EEM)
      19. 5.10.19 Peripheral File Map
    11. 5.11 Input/Output Diagrams
      1. 5.11.1 Port P1 Input/Output With Schmitt Trigger
      2. 5.11.2 Port P2 Input/Output With Schmitt Trigger
      3. 5.11.3 Port P3 Input/Output With Schmitt Trigger
      4. 5.11.4 Port P4 Input/Output With Schmitt Trigger
      5. 5.11.5 Port P5 Input/Output With Schmitt Trigger
      6. 5.11.6 Port P6 Input/Output With Schmitt Trigger
    12. 5.12 Device Descriptors (TLV)
    13. 5.13 Identification
      1. 5.13.1 Revision Identification
      2. 5.13.2 Device Identification
      3. 5.13.3 JTAG Identification
  6. 6Applications, Implementation, and Layout
    1. 6.1 Device Connection and Layout Fundamentals
      1. 6.1.1 Power Supply Decoupling and Bulk Capacitors
      2. 6.1.2 External Oscillator
      3. 6.1.3 JTAG
      4. 6.1.4 Reset
      5. 6.1.5 Unused Pins
      6. 6.1.6 General Layout Recommendations
      7. 6.1.7 Do's and Don'ts
    2. 6.2 Peripheral- and Interface-Specific Design Information
      1. 6.2.1 ADC Peripheral
        1. 6.2.1.1 Partial Schematic
        2. 6.2.1.2 Design Requirements
        3. 6.2.1.3 Layout Guidelines
    3. 6.3 ROM Libraries
    4. 6.4 Typical Applications
  7. 7器件和文档支持
    1. 7.1 使用入门
    2. 7.2 器件命名规则
    3. 7.3 工具和软件
    4. 7.4 文档支持
    5. 7.5 相关链接
    6. 7.6 商标
    7. 7.7 静电放电警告
    8. 7.8 Glossary
  8. 8机械、封装和可订购信息

5.10.9 Timers (Timer0_B3, Timer1_B3, Timer2_B3, Timer3_B7)

The Timer0_B3, Timer1_B3, and Timer2_B3 modules are 16-bit timers and counters with three capture/compare registers each. Timer3_B7 is a 16-bit timers with seven capture/compare registers each. Each can support multiple captures or compares, PWM outputs, and interval timing (see Table 5-16, Table 5-17, Table 5-18, and Table 5-19). Each has extensive interrupt capabilities. Interrupts can be generated from the counter on overflow conditions and from each of the capture/compare registers. The CCR0 registers on all timers are not externally connected and can only be used for hardware period timing and interrupt generation. In Up Mode, they can be used to set the overflow value of the counter.

Table 5-16 Timer0_B3 Signal Connections

PORT PIN DEVICE INPUT SIGNAL MODULE INPUT NAME MODULE BLOCK MODULE OUTPUT SIGNAL DEVICE OUTPUT SIGNAL
P2.7 TB0CLK TBCLK Timer N/A
ACLK (internal) ACLK
SMCLK (internal) SMCLK
N/A INCLK
From RTC (internal) CCI0A CCR0 TB0 Not used
ACLK (internal) CCI0B Timer1_B3 CCI0B input
DVSS GND
DVCC VCC
P1.6 TB0.1 CCI1A CCR1 TB1 TB0.1
From eCOMP0.O (internal) CCI1B Timer1_B3 CCI1B input
DVSS GND
DVCC VCC
P1.7 TB0.2 CCI2A CCR2 TB2 TB0.2
N/A CCI2B Timer1_B3 INCLK
Timer1_B3 CCI2B input,
IR carrier input
DVSS GND
DVCC VCC

Table 5-17 Timer1_B3 Signal Connections

PORT PIN DEVICE INPUT SIGNAL MODULE INPUT NAME MODULE BLOCK MODULE OUTPUT SIGNAL DEVICE OUTPUT SIGNAL
P2.2 TB1CLK TBCLK Timer N/A
ACLK (internal) ACLK
SMCLK (internal) SMCLK
Timer0_B3 CCR2B output (internal) INCLK
Timer3_B7 CCR0B output (internal) CCI0A CCR0 TB0 Not used
Timer0_B3 CCR0B output (internal) CCI0B Not used
DVSS GND
DVCC VCC
P2.0 TB1.1 CCI1A CCR1 TB1 TB1.1
Timer0_B3 CCR1B output (internal) CCI1B To ADC trigger
DVSS GND
DVCC VCC
P2.1 TB1.2 CCI2A CCR2 TB2 TB1.2
Timer0_B3 CCR2B output (internal) CCI2B IR coding input
DVSS GND
DVCC VCC

Table 5-18 Timer2_B3 Signal Connections

PORT PIN DEVICE INPUT SIGNAL MODULE INPUT NAME MODULE BLOCK MODULE OUTPUT SIGNAL DEVICE OUTPUT SIGNAL
P2.7 TB2CLK TBCLK Timer N/A
ACLK (internal) ACLK
SMCLK (internal) SMCLK
TB2CLK INCLK
Not used CCI0A CCR0 TB0 Not used
DVSS GND
DVCC VCC
MFM Complete Event CCI0B MFM start trigger
P5.0 TB2.1 CCI1A CCR1 TB1 TB2.1
From eCOMP1.O (internal) CCI1B To SAC DAC update trigger 10b(1)
DVSS GND
DVCC VCC
P5.1 TB2.2 CCI2A CCR2 TB2 TB2.2
Not used CCI2B To SAC DAC update trigger 11b(1)
DVSS GND
DVCC VCC
(1) MSP430FR235x devices only

Table 5-19 Timer3_B7 Signal Connections

PORT PIN DEVICE INPUT SIGNAL MODULE INPUT NAME MODULE BLOCK MODULE OUTPUT SIGNAL DEVICE OUTPUT SIGNAL
P6.6 TB3CLK TBCLK Timer N/A
ACLK (internal) ACLK
SMCLK (internal) SMCLK
TB3CLK INCLK
Not used CCI0A CCR0 TB0 Not used
Not used CCI0B To Timer1_B3 CCI0A
DVSS GND
DVCC VCC
P6.0 TB3.1 CCI1A CCR1 TB1 TB3.1
Not used CCI1B
DVSS GND
DVCC VCC
P6.1 TB3.2 CCI2A CCR2 TB2 TB3.2
P4.0 ISORXD CCI2B AND UCA1TXD ISOTXD
DVSS GND
DVCC VCC
P6.2 TB3.3 CCI3A CCR3 TB3 TB3.3
Not used CCI3B
DVSS GND
DVCC VCC
P6.3 TB3.4 CCI4A CCR4 TB4 TB3.4
Not used CCI4B Not used
DVSS GND
DVCC VCC
P6.4 TB3.5 CCI5A CCR5 TB5 TB3.5
Not used CCI5B Not used
DVSS GND
DVCC VCC
P6.5 TB3.6 CCI6A CCR6 TB6 TB3.6
Not used CCI6B Not used
DVSS GND
DVCC VCC

The interconnection of Timer0_B3 and Timer1_B3 can be used to modulate the eUSCI_A pin of UCA0TXD/UCA0SIMO in either ASK or FSK mode, with which a user can easily acquire a modulated infrared command for directly driving an external IR diode. The IR functions are fully controlled by SYS configuration registers 1 including IREN (enable), IRPSEL (polarity select), IRMSEL (mode select), IRDSSEL (data select), and IRDATA (data) bits. For more information, see the SYS chapter in the MSP430FR4xx and MSP430FR2xx Family User's Guide.

The Timer_B module feature the function to put Timer_B all outputs into a high impedance state when the selected source is triggered. The source can be selected from external pin or internal of the device, it is controlled by TBxTRG in SYS. For more information, see the SYS chapter in the MSP430FR4xx and MSP430FR2xx Family User's Guide.

The Timer2_B3 CCR0 is tied with the Manchester function module (MFM).

Table 5-20 lists the Timer_B high-impedance trigger sources.

Table 5-20 TBxOUTH

TBxTRGSEL TBxOUTH TRIGGER SOURCE SELECTION TIMER_B PAD OUTPUT HIGH IMPEDANCE
TB0TRGSEL = 0 eCOMP0 output (internal) P1.6, P1.7
TB0TRGSEL= 1 P1.2
TB1TRGSEL = 0 eCOMP0 output (internal) P2.0, P2.1
TB1TRGSEL = 1 P2.3
TB2TRGSEL = 0 eCOMP1 output (internal) P5.0, P5.1
TB2TRGSEL = 1 P5.3
TB3TRGSEL = 0 eCOMP1 output (internal) P6.0, P6.1, P6.2, P6.3, P6.4, P6.5
TB3TRGSEL = 1 N/A
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