米6体育平台手机版

6.6 AC Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.

PARAMETER		TEST CONDITIONS	PIN/FREQ.	MIN	TYP	MAX	UNIT
GPIO BIT RATE
R_b,FC	Forward channel bit rate	PCLK = 25 MHz - 170 MHz⁽²⁾	GPIO[3:0]		0.25 × PCLK		Mbps
R_b,BC	Back channel bit rate		GPIO[3:0]		133		kbps
R_b,BC	Back channel bit rate	High speed (2-lane mode), 1 D_GPIO active See Table 3	D_GPIO[3:0]		2		Mbps
		High speed (2-lane mode), 2 D_GPIOs active See Table 3.			1.33		Mbps
		High speed (2-lane mode), 4 D_GPIOs active See Table 3			800		kbps
		Normal mode — see Table 3			133		kbps
t_GPIO,FC	GPIO pulse width, forward channel		GPIO[3:0]	> 2 / PCLK⁽²⁾			s
t_GPIO,BC	GPIO pulse width, back channel		GPIO[3:0]	20			μs
RESET
t_LRST	PDB reset low pulse		PDB	2			ms
LOOP-THROUGH MONITOR OUTPUT
E_W	Differential output eye opening width	R_L = 100 Ω, jitter frequency > PCLK⁽²⁾ / 40 See Figure 2	CMLOUTP, CMLOUTN		0.4		UI⁽³⁾
E_H	Differential output eye height	R_L = 100 Ω, jitter frequency > PCLK⁽²⁾ / 40 See Figure 2	CMLOUTP, CMLOUTN		> 300		mV
FPD-LINK III INPUT
t_DDLT	Lock time	See Figure 4	RIN0+, RIN0–, RIN1+, RIN1–		5	10	ms
t_IJIT	Input jitter	Single Lane PCLK = 96 MHz f_JIT > PCLK/20 BER < 1E-10 10-m DACAR535-2 STQ	RIN0+, RIN0–, RIN1+, RIN1–			0.3	UI⁽³⁾
t_IJIT	Input jitter	Dual Lane PCLK = 170 MHz f_JIT > PCLK/20 BER < 1E-10 10-m DACAR535-2 STQ	RIN0+, RIN0–, RIN1+, RIN1–			0.3	UI⁽³⁾
I2S TRANSMITTER
t_J,I2S	Clock output jitter		I2S_CLK		2		ns
t_I2S	I2S clock period⁽¹⁾	See Figure 9			>2 / PCLK⁽²⁾ or >77		ns
t_HC,I2S	I2S clock high time⁽¹⁾	See Figure 9			0.48		t_I2S
t_LC,I2S	I2S clock low time⁽¹⁾	See Figure 9			0.48		t_I2S
t_SR,I2S	I2S set-up time	See Figure 9	I2S_DA, I2S_DB, I2S_DC, I2S_DD		0.4		t_I2S
t_HR,I2S	I2S hold time	See Figure 9	I2S_DA, I2S_DB, I2S_DC, I2S_DD		0.4		t_I2S

(1) I2S specifications for t_LC,I2S and t_HC,I2S pulses must each be greater than 1 period to ensure sampling and supersedes the 0.35 × t_I2S requirement. t_LC,I2S and t_HC,I2S must be longer than the greater of either 0.35 × t_I2S or 2 × PCLK.

(2) PCLK refers to the equivalent pixel clock frequency, which is equal to the FPD-Link III line rate / 35.

(3) UI – Unit Interval is equivalent to one serialized data bit width. For Single Lane mode 1UI = 1 / (35*PCLK). For Dual Lane mode, 1UI = 1 / (35*PCLK/2). The UI scales with PCLK frequency.