ZHCSIJ3C June 2008 – July 2018 ADS7950 , ADS7951 , ADS7952 , ADS7953 , ADS7954 , ADS7955 , ADS7956 , ADS7957 , ADS7958 , ADS7959 , ADS7960 , ADS7961
PRODUCTION DATA.
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| ANALOG INPUT | ||||||
| Full-scale input span(1) | Range 1 | 0 | VREF | V | ||
| Range 2 while 2xVREF ≤ +VA | 0 | 2*VREF | ||||
| Absolute input range | Range 1 | –0.20 | VREF + 0.2 | V | ||
| Range 2 while 2xVREF ≤ +VA | –0.20 | 2*VREF + 0.2 | ||||
| Input capacitance | 15 | pF | ||||
| Input leakage current | TA = 125°C | 61 | nA | |||
| SYSTEM PERFORMANCE | ||||||
| Resolution | 8 | Bits | ||||
| No missing codes | 8 | Bits | ||||
| Integral linearity | –0.3 | ±0.1 | 0.3 | LSB(2) | ||
| Differential linearity | –0.3 | ±0.1 | 0.3 | LSB | ||
| Offset error(3) | –0.5 | ±0.2 | 0.5 | LSB | ||
| Gain error | Range 1 | –0.6 | ±0.1 | 0.6 | LSB | |
| Range 2 | ±0.1 | |||||
| SAMPLING DYNAMICS | ||||||
| Conversion time | 20 MHz SCLK | 800 | ns | |||
| Acquisition time | 325 | ns | ||||
| Maximum throughput rate | 20 MHz SCLK | 1 | MHz | |||
| Aperture delay | 5 | ns | ||||
| Step response | 150 | ns | ||||
| Overvoltage recovery | 150 | ns | ||||
| DYNAMIC CHARACTERISTICS | ||||||
| Total harmonic distortion(4) | 100 kHz | –75 | dB | |||
| Signal-to-noise ratio | 100 kHz | 49 | dB | |||
| Signal-to-noise + distortion | 100 kHz | 49 | ||||
| Spurious free dynamic range | 100 kHz | –78 | dB | |||
| Full power bandwidth | At –3 dB | 47 | MHz | |||
| Channel-to-channel crosstalk | Any off-channel with 100 kHz, Full-scale input to channel being sampled with DC input. | –95 | dB | |||
| From previously sampled to channel with 100 kHz, Full-scale input to channel being sampled with DC input. | –85 | |||||
| EXTERNAL REFERENCE INPUT | ||||||
| VREF reference voltage at REFP | 2 | 2.5 | 3 | V | ||
| Reference input resistance | fsample = 1 MHz | 100 | kΩ | |||
| ALARM SETTING | ||||||
| High threshold range | 000 | 255 | LSB | |||
| Low threshold range | 000 | 255 | LSB | |||
| DIGITAL INPUT/OUTPUT | ||||||
| Logic family | CMOS | |||||
| Logic level | VIH | 0.7*(+VBD) | V | |||
| VIL | +VBD = 5 V | 0.8 | ||||
| VIL | +VBD = 3 V | 0.4 | ||||
| VOH | At Isource = 200 μA | +VBD-0.2 | ||||
| VOL | At Isink = 200 μA | 0.4 | ||||
| Data format | MSB First | |||||
| POWER SUPPLY REQUIREMENTS | ||||||
| +VA supply voltage | 2.7 | 3.3 | 5.25 | V | ||
| +VBD supply voltage | 1.7 | 3.3 | 5.25 | V | ||
| Supply current (normal mode) | At +VA = 2.7 to 3.6 V and 1 MHz throughput | 1.8 | mA | |||
| At +VA = 2.7 to 3.6 V static state | 1.05 | |||||
| At +VA = 4.7 to 5.25 V and 1 MHz throughput | 2.3 | 3 | ||||
| At +VA = 4.7 to 5.25 V static state | 1.1 | 1.5 | ||||
| Power-down state supply current | 1 | μA | ||||
| +VBD supply current | +VA = 5.25V, fs = 1MHz | 1 | mA | |||
| Power-up time | 1 | μs | ||||
| Invalid conversions after power up or reset | 1 | Conversion | ||||