米6体育平台手机版

ZHCSIJ5C August 2018 – June 2019 ADS9224R , ADS9234R

PRODUCTION DATA.

6.9 Switching Characteristics

at AVDD = 4.5 V to 5.5V, DVDD = 2.35 V to 5.5 V, V_CM = V_REF/2, Internal reference and maximum throughput (unless otherwise noted); minimum and maximum values at T_A = -40℃ to +125℃; typical values at T_A = 25℃, AVDD = 5V, DVDD = 3.3 V

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
CONVERSION CONTROL AND DATA TRANSFER (See Figure 1 and Figure 2)
t_DRDY	Data ready time for present sample: CONVST high to READY high	Zero cycle latency (zone 1 transfer) for ADS9224R			315	ns
t_DRDY	Data ready time for present sample: CONVST high to READY high	Zero cycle latency (zone 1 transfer) for ADS9234R			280	ns
SPI-COMPATIBLE AND PARALLEL BYTE PROTOCOL (See Figure 3)
t_{DEN_CSDO}	Delay time: CS falling to data valid on SDO-x				12	ns
t_{DZ_CSDO}	Delay time: CS rising edge to SDO-x tristate				12	ns
t_{D_CKDO}	Delay time: SCLK launch edge to next data valid on SDO-x	SPI-compatible protocols with single data rate			15.8	ns
t_{D_CKDO}	Delay time: SCLK launch edge to next data valid on SDO-x	SPI-compatible protocols with double data rate			21	ns
t_{D_CKDO}	Delay time: SCLK launch edge to next data valid on SDO-x	Parallel byte protocol			21	ns
t_A	Aperture delay			8		ns
t_A	t_A mismatch			40		ps
t_JITTER	Aperture jitter			2		ps
CLOCK RE-TIMER PROTOCOL WITH STROBE = SCLK (EXTERNAL CLOCK)⁽¹⁾(See Figure 4)
t_{OFF_STROBE_DO}	Time offset: STROBE edge to next data valid on SDO-x		-2.5		2.5	ns
t_{D_CS_READY}	Delay time: CS rising to READY displaying internal device state				13.5	ns
t_{D_CKSTROBE_r}	Delay time: SCLK rising edge to STROBE rising				21.5	ns
t_{D_CKSTROBE_f}	Delay time: SCLK falling edge to STROBE falling				21.5	ns
t_{PH_STROBE}	Strobe output high time		0.45 × t_STR		0.55 × t_STR	ns
t_{PL_STROBE}	Strobe output low time		0.45 × t_STR		0.55 × t_STR	ns
CLOCK RE-TIMER PROTOCOL WITH STROBE = INTERNAL CLOCK ⁽¹⁾(See Figure 5)
t_{D_CS_STROBE}	Delay time : CS falling to 1^st STROBE rising		15		50	ns
t_{OFF_STROBE_DO}	Time offset : STROBE edge to next data valid on SDO-x		-2.5		2.5	ns
t_{D_CS_READY}	Delay time: CS rising to READY displaying internal device state				13.5	ns
t_INTCLK	INTCLK period			15		ns
t_STR	STROBE period	INTCLK		16		ns
		INTCLK / 2		30		ns
		INTCLK / 4		60		ns
t_{WH_STR}	STROBE high period		0.45 × t_STR		0.55 × t_STR	ns
t_{WL_STR}	STROBE low period		0.45 × t_STR		0.55 × t_STR	ns
ASYNCHRONOUS RESET AND POWER-DOWN TIMING (See Figure 6)
t_RST-WKUP	Wake up time from reset				1	µs
t_PD-WKUP⁽¹⁾	Wake up time from power-down			18	150	ms
t_WKUP-REFOUT	REFOUT wake-up time			15.6	140	ms
t_{REFP_x-SETTLE}	Reference buffer output settling time	C_{REFP_x} = 10µF		18	150	ms

(1) With C_{REFP_x} = 10µF

ADS9224R ADS9234R timing-conv-zone1-sbas876.gif

1. The READY output is required for data transfer with zero cycle latency. The STROBE output is required only for clock re-timer (CRT) protocols.

Figure 1. Conversion Control and Data Transfer With Zero Cycle Latency (Zone 1 Transfer)

ADS9224R ADS9234R timing-conv-zone2-sbas876.gif

1. The READY output is not required for zone 2 data transfer. The STROBE output is required only for clock re-timer protocols.

Figure 2. Conversion Control and Data Transfer With Wider Read Cycle (Zone 2 Transfer)

ADS9224R ADS9234R timing-spi-sbas876.gif

1. The SCLK polarity, launch edge, and capture edge depend on the SPI protocol selected. DDR is not supported with the parallel byte protocol.

Figure 3. SPI-Compatible and Parallel Byte Protocols Timing

ADS9224R ADS9234R timing-crt-ext-SBAS876.gif

Figure 4. Clock Re-Timer Protocol (External Clock) Timing

ADS9224R ADS9234R timing-crt-int-SBAS876.gif

Figure 5. Clock Re-Timer Protocol (Internal Clock) Timing

ADS9224R ADS9234R timing_rst_pd_sbas842.gif

Figure 6. Asynchronous Reset and Power-Down Timing