ZHCSIJ5C August   2018  – June 2019 ADS9224R , ADS9234R

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      典型应用图
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: ADS92x4R
    6. 6.6  Electrical Characteristics: ADS9224R
    7. 6.7  Electrical Characteristics: ADS9234R
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 Typical Characteristics: ADS9224R
    11. 6.11 Typical Characteristics: ADS9234R
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Converter Modules
        1. 7.3.1.1 Analog Input With Sample-and-Hold
        2. 7.3.1.2 ADC Transfer Function
      2. 7.3.2 Internal Reference Voltage
      3. 7.3.3 Reference Buffers
      4. 7.3.4 REFby2 Buffer
      5. 7.3.5 Data Averaging
        1. 7.3.5.1 Averaging of Two Samples
        2. 7.3.5.2 Averaging of Four Samples
    4. 7.4 Device Functional Modes
      1. 7.4.1 ACQ State
      2. 7.4.2 CNV State
      3. 7.4.3 Reset or Power-Down
        1. 7.4.3.1 Reset
        2. 7.4.3.2 Power-Down
      4. 7.4.4 Conversion Control and Data Transfer Frame
        1. 7.4.4.1 Conversion Control and Data Transfer Frame With Zero Cycle Latency (Zone 1 Transfer)
        2. 7.4.4.2 Conversion Control and Data Transfer Frame With Wide Read Cycle (Zone 2 Transfer)
    5. 7.5 READY/STROBE Output
      1. 7.5.1 READY Output
      2. 7.5.2 STROBE Output
    6. 7.6 Programming
      1. 7.6.1 Output Data Word
      2. 7.6.2 Data Transfer Protocols
        1. 7.6.2.1 Protocols for Reading From the Device
          1. 7.6.2.1.1 Legacy, SPI-Compatible Protocols (SPI-xy-S-SDR)
          2. 7.6.2.1.2 SPI-Compatible Protocols With Bus Width Options and Single Data Rate (SPI-xy-D-SDR and SPI-xy-Q-SDR)
          3. 7.6.2.1.3 SPI-Compatible Protocols With Bus Width Options and Double Data Rate (SPI-x1-S-DDR, SPI-x1-D-DDR, SPI-x1-Q-DDR)
          4. 7.6.2.1.4 Clock Re-Timer (CRT) Protocols (CRT-S-SDR, CRT-D-SDR, CRT-Q-SDR, CRT-S-DDR, CRT-D-DDR, CRT-Q-DDR)
          5. 7.6.2.1.5 Parallel Byte Protocols (PB-xy-AB-SDR, PB-xy-AA-SDR)
        2. 7.6.2.2 Device Setup
          1. 7.6.2.2.1 Single Device: All Enhanced-SPI Options
          2. 7.6.2.2.2 Single Device: Minimum Pins for a Standard SPI Interface
        3. 7.6.2.3 Protocols for Configuring the Device
      3. 7.6.3 Reading and Writing Registers
    7. 7.7 Register Maps
      1. 7.7.1 ADS92x4R Registers
        1. 7.7.1.1 DEVICE_STATUS Register (Offset = 0h) [reset = 0h]
          1. Table 12. DEVICE_STATUS Register Field Descriptions
        2. 7.7.1.2 POWER_DOWN_CFG Register (Offset = 1h) [reset = 0h]
          1. Table 13. POWER_DOWN_CFG Register Field Descriptions
        3. 7.7.1.3 PROTOCOL_CFG Register (Offset = 2h) [reset = 0h]
          1. Table 14. PROTOCOL_CFG Register Field Descriptions
        4. 7.7.1.4 BUS_WIDTH Register (Offset = 3h) [reset = 0h]
          1. Table 15. BUS_WIDTH Register Field Descriptions
        5. 7.7.1.5 CRT_CFG Register (Offset = 4h) [reset = 0h]
          1. Table 16. CRT_CFG Register Field Descriptions
        6. 7.7.1.6 OUTPUT_DATA_WORD_CFG Register (Offset = 5h) [reset = 0h]
          1. Table 17. OUTPUT_DATA_WORD_CFG Register Field Descriptions
        7. 7.7.1.7 DATA_AVG_CFG Register (Offset = 6h) [reset = 0h]
          1. Table 18. DATA_AVG_CFG Register Field Descriptions
        8. 7.7.1.8 REFBY2_OFFSET Register (Offset = 7h) [reset = 0h]
          1. Table 19. REFBY2_OFFSET Register Field Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 ADC Input Driver
        1. 8.1.1.1 Charge-Kickback Filter
      2. 8.1.2 Input Amplifier Selection
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Signal Path
      2. 10.1.2 Grounding and PCB Stack-Up
      3. 10.1.3 Decoupling of Power Supplies
      4. 10.1.4 Reference Decoupling
      5. 10.1.5 Differential Input Decoupling
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 开发支持
    2. 11.2 相关文档
    3. 11.3 相关链接
    4. 11.4 接收文档更新通知
    5. 11.5 社区资源
    6. 11.6 商标
    7. 11.7 静电放电警告
    8. 11.8 Glossary
  12. 12机械、封装和可订购信息

5 Pin Configuration and Functions

RHB Package
5-mm × 5-mm, 32-Pin VQFN
Top View

Pin Functions

PIN FUNCTION DESCRIPTION
NAME NO.
AINM_A 2 Analog input Negative analog input for channel A.
AINM_B 7 Analog input Negative analog input for channel B.
AINP_A 1 Analog input Positive analog input for channel A.
AINP_B 8 Analog input Positive analog input for channel B.
AVDD 12, 29 Power supply Analog power-supply pin.
Connect a 1-µF decoupling capacitor between pin 12 and pin 11.
Connect a 1-µF decoupling capacitor between pin 29 and pin 30.
CONVST 13 Digital input Conversion start input pin.
A CONVST rising edge starts the conversion for ADC_A and ADC_B.
CS 14 Digital input Chip-select input pin; active low.
The host and device can communicate when CS is low.
The SDO-x pins go to Hi-Z when CS is high.
DVDD 28 Power supply Interface power-supply pin.
Connect a 1-µF decoupling capacitor between pin 27 and pin 28.
GND 4, 11, 27, 30 Power supply Ground
NC 6 — No external connection
PD/RST 26 Digital input Asynchronous reset or power-down input pin.
See the Reset or Power-Down section.
READY/STROBE 25 Digital output Indicates data ready or strobe output for data capture.
REFby2 3 Analog output REFby2 buffer output.
Connect a 1-µF decoupling capacitor between pin 3 and pin 4.
REFOUT 5 Analog output Internal reference output.
Connect a 1-µF decoupling capacitor between pin 5 and pin 4.
REFM_A 32 Analog output Negative output of reference buffer A. Negative reference input for ADC_A.
Externally connect to the device GND.
REFM_B 9 Analog output Negative output of reference buffer B. Negative reference input for ADC_B.
Externally connect to the device GND.
REFP_A 31 Analog output Positive output of reference buffer A. Positive reference input for ADC_A.
Connect a 10-µF decoupling capacitor between pin 31 and pin 32.
REFP_B 10 Analog output Positive output of reference buffer B. Positive reference input for ADC_B.
Connect a 10-µF decoupling capacitor between pin 9 and pin 10.
SCLK 16 Digital input Clock input pin for the serial interface.
SDI 15 Digital input Serial data input pin.
This pin is used to program the device registers.
SDO-0/0A 24 Digital output SPI mode: data output 0 for channel A.
Parallel byte mode: least significant bit (LSB) from the data byte.
SDO-1/1A 23 Digital output SPI mode: data output 1 for channel A.
Parallel byte mode: LSB+1 from the data byte.
SDO-2/2A 22 Digital output SPI mode: data output 2 for channel A.
Parallel byte mode: LSB+2 from the data byte.
SDO-3/3A 21 Digital output SPI mode: data output 3 for channel A.
Parallel byte mode: LSB+3 from the data byte.
SDO-4/0B 20 Digital output SPI mode: data output 0 for channel B.
Parallel byte mode: LSB+4 from the data byte.
SDO-5/1B 19 Digital output SPI mode: data output 1 for channel B.
Parallel byte mode: LSB+5 from the data byte.
SDO-6/2B 18 Digital output SPI mode: data output 2 for channel B.
Parallel byte mode: LSB+6 from the data byte.
SDO-7/3B 17 Digital output SPI mode: data output 3 for channel B.
Parallel byte mode: most significant bit (MSB) from the data byte.
Thermal pad Power supply Exposed thermal pad. TI recommends connecting this pin to the printed circuit board (PCB) ground.
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