11.1.4 Switch-Node Capacitance

GaN devices have very low output capacitance and switch quickly with a high dv/dt, yielding very low switching loss. To preserve this low switching loss, additional capacitance added to the output node must be minimized. The PCB capacitance at the switch node can be minimized by following these guidelines:

• Minimize overlap between the switch-node plane and other power and ground planes
• Thin the GND return path under the high-side device somewhat while still maintaining a low-inductance path
• Choose high-side isolator ICs and bootstrap diodes with low capacitance
• Locate the power inductor as close to the power stage as possible
• Power inductors should be constructed with a single-layer winding to minimize intra-winding capacitance
• If a single-layer inductor is not possible, consider placing a small inductor between the primary inductor and the power stage to effectively shield the power stage from the additional capacitance
• If a back-side heat-sink is used, restrict the switch-node copper coverage on the bottom copper layer to the minimum area necessary to extract the needed heat