米6体育平台手机版

ZHCSIP8B August 2018 – April 2020 AMC1035

PRODUCTION DATA.

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
f_CLKIN	CLKIN clock frequency	MCE = 0	9	20	21	MHz
f_CLKIN	CLKIN clock frequency	MCE = 1	9	10	11	MHz
Duty_Cycle	CLKIN clock duty cycle⁽¹⁾		40%	50%	60%
t_H1	DOUT hold time after rising edge of CLKIN	MCE = 0, C_LOAD = 15 pF	6			ns
t_H2	DOUT hold time after rising edge of CLKIN	MCE = 1, C_LOAD = 15 pF	6		23	ns
t_H3	DOUT hold time after falling edge of CLKIN	MCE = 1, C_LOAD = 15 pF	10		26	ns
t_D1	Rising edge of CLKIN to DOUT valid delay	MCE = 0, C_LOAD = 15 pF			25	ns
t_D2	Rising edge of CLKIN to DOUT valid delay	MCE = 1, C_LOAD = 15 pF	11		27	ns
t_D3	Falling edge of CLKIN to DOUT valid delay	MCE = 1, C_LOAD = 15 pF	15		30	ns
t_r	DOUT rise time	10% to 90%, 3.0 V ≤ VDD ≤ 3.6 V, C_LOAD = 15 pF		2.5	5	ns
t_r	DOUT rise time	10% to 90%, 4.5 V ≤ VDD ≤ 5.5 V, C_LOAD = 15 pF		1.5	3.5	ns
t_f	DOUT fall time	90% to 10%, 3.0 V ≤ VDD ≤ 3.6 V, C_LOAD = 15 pF		2.5	5.8	ns
t_f	DOUT fall time	90% to 10%, 4.5 V ≤ VDD ≤ 5.5 V, C_LOAD = 15 pF		1.8	4.4	ns
t_ASTART	Analog startup time	VDD step to 3.0 V, 0.1% settling, CLKIN applied		0.25		ms

(1) The duty cycle of DOUT equals the clock duty cycle of the applied CLKIN signal.

Figure 1. Digital Interface Timing

Figure 2. Device Startup Timing