ZHCSIU3 September 2018 ADS1235
PRODUCTION DATA.
The register map consists of 18, one-byte registers. Collectively, the registers are used to configure the ADC to the desired operating mode. Access the registers by using the RREG and WREG (read-register and write-register) commands. Register data are accessed one register byte at a time for each command operation. At power-on or device reset, the registers are reset to the default values, as shown in the Default column of Table 27. Writing new data to certain registers causes the ADC conversion in progress to restart. The affected registers are listed in the Restart column in Table 27.
Register-write access is enabled or disabled by the UNLOCK and LOCK commands, respectively. The default mode is register UNLOCK. See the LOCK Command section for more details.
| (rrh) | REGISTER | DEFAULT | RESTART | BIT 7 | BIT 6 | BIT 5 | BIT 4 | BIT 3 | BIT 2 | BIT 1 | BIT 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|
| 00h | ID | Cxh | DEV_ID[3:0] | REV_ID[3:0] | |||||||
| 01h | STATUS | 01h | LOCK | CRCERR | PGAL_ALM | PGAH_ALM | REFL_ALM | DRDY | CLOCK | RESET | |
| 02h | MODE0 | 24h | Yes | 0 | DR[3:0] | FILTER[2:0] | |||||
| 03h | MODE1 | 01h | Yes | 0 | CHOP[1:0] | CONVRT | DELAY[3:0] | ||||
| 04h | MODE2 | 00h | GPIO_CON[3:0] | GPIO_DIR[3:0] | |||||||
| 05h | MODE3 | 00h | PWDN | STATENB | CRCENB | SPITIM | GPIO_DAT[3:0] | ||||
| 06h | REF | 05h | Yes | 0 | 0 | 0 | 0 | RMUXP[1:0] | RMUXN[1:0] | ||
| 07h | OFCAL0 | 00h | OFC[7:0] | ||||||||
| 08h | OFCAL1 | 00h | OFC[15:8] | ||||||||
| 09h | OFCAL2 | 00h | OFC[23:16] | ||||||||
| 0Ah | FSCAL0 | 00h | FSC[7:0] | ||||||||
| 0Bh | FSCAL1 | 00h | FSC[15:8] | ||||||||
| 0Ch | FSCAL2 | 40h | FSC[23:16] | ||||||||
| 0Dh | RESERVED | FFh | FFh | ||||||||
| 0Eh | RESERVED | 00h | 00h | ||||||||
| 0Fh | RESERVED | 00h | 00h | ||||||||
| 10h | PGA | 00h | Yes | BYPASS | 0 | 0 | 0 | 0 | GAIN[2:0] | ||
| 11h | INPMUX | FFh | Yes | MUXP[3:0] | MUXN[3:0] | ||||||