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ZHCSIZ5E October 2018 – June 2021 IWR6443 , IWR6843

PRODUCTION DATA

8.10.3.3.1 SPI Slave Mode Switching Parameters (SPICLK = input, SPISIMO = input,
and SPISOMI = output)⁽¹⁾⁽²⁾⁽³⁾

NO.	PARAMETER		MIN	MAX	UNIT
1	t_c(SPC)S	Cycle time, SPICLK⁽⁴⁾	25		ns
2⁽⁵⁾	t_w(SPCH)S	Pulse duration, SPICLK high (clock polarity = 0)	10		ns
2⁽⁵⁾	t_w(SPCL)S	Pulse duration, SPICLK low (clock polarity = 1)	10		ns
3⁽⁵⁾	t_w(SPCL)S	Pulse duration, SPICLK low (clock polarity = 0)	10		ns
3⁽⁵⁾	t_w(SPCH)S	Pulse duration, SPICLK high (clock polarity = 1)	10		ns
4⁽⁵⁾	t_{d(SPCH-SOMI)S}	Delay time, SPISOMI valid after SPICLK high (clock polarity = 0)		10	ns
4⁽⁵⁾	t_{d(SPCL-SOMI)S}	Delay time, SPISOMI valid after SPICLK low (clock polarity = 1)		10	ns
5⁽⁵⁾	t_{h(SPCH-SOMI)S}	Hold time, SPISOMI data valid after SPICLK high (clock polarity = 0)	2		ns
5⁽⁵⁾	t_{h(SPCL-SOMI)S}	Hold time, SPISOMI data valid after SPICLK low (clock polarity = 1)	2		ns
4⁽⁵⁾	t_{d(SPCH-SOMI)S}	Delay time, SPISOMI valid after SPICLK high (clock polarity = 0; clock phase = 0) OR (clock polarity = 1; clock phase = 1)		10	ns
4⁽⁵⁾	t_{d(SPCL-SOMI)S}	Delay time, SPISOMI valid after SPICLK low (clock polarity = 1; clock phase = 0) OR (clock polarity = 0; clock phase = 1)		10	ns
5⁽⁵⁾	t_{h(SPCH-SOMI)S}	Hold time, SPISOMI data valid after SPICLK high (clock polarity = 0; clock phase = 0) OR (clock polarity = 1; clock phase = 1)	2		ns
5⁽⁵⁾	t_{h(SPCL-SOMI)S}	Hold time, SPISOMI data valid after SPICLK low (clock polarity = 1; clock phase = 0) OR (clock polarity = 0; clock phase = 1)	2		ns
6⁽⁵⁾	t_{su(SIMO-SPCL)S}	Setup time, SPISIMO before SPICLK low (clock polarity = 0; clock phase = 0) OR (clock polarity = 1; clock phase = 1)	3		ns
6⁽⁵⁾	t_{su(SIMO-SPCH)S}	Setup time, SPISIMO before SPICLK high (clock polarity = 1; clock phase = 0) OR (clock polarity = 0; clock phase = 1)	3		ns
7⁽⁵⁾	t_{h(SPCL-SIMO)S}	Hold time, SPISIMO data valid after SPICLK low (clock polarity = 0; clock phase = 0) OR (clock polarity = 1; clock phase = 1)	1		ns
7⁽⁵⁾	t_{h(SPCL-SIMO)S}	Hold time, SPISIMO data valid after SPICLK high (clock polarity = 1; clock phase = 0) OR (clock polarity = 0; clock phase = 1)	1		ns

(1) The MASTER bit (SPIGCRx.0) is cleared ( where x = 0 or 1 ).

(2) The CLOCK PHASE bit (SPIFMTx.16) is either cleared or set for CLOCK PHASE = 0 or CLOCK PHASE = 1 respectively.

(3) t_{c(MSS_VCLK)} = main subsystem clock time = 1 / f_{(MSS_VCLK)}. For more details, see the Technical Reference Manual.

(4) When the SPI is in Slave mode, the following must be true: For PS values from 1 to 255: t_c(SPC)S ≥ (PS +1)t_{c(MSS_VCLK)} ≥ 25 ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.For PS values of 0: t_c(SPC)S = 2t_{c(MSS_VCLK)} ≥ 25 ns.

(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).

Figure 8-8 SPI Slave Mode External Timing (CLOCK PHASE = 0)

Figure 8-9 SPI Slave Mode External Timing (CLOCK PHASE = 1)

8.10.3.3.1 SPI Slave Mode Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output)(1)(2)(3)

8.10.3.3.1 SPI Slave Mode Switching Parameters (SPICLK = input, SPISIMO = input,
and SPISOMI = output)⁽¹⁾⁽²⁾⁽³⁾