ZHCSIZ5E October   2018  – June 2021 IWR6443 , IWR6843

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 功能方框图
  5. 5 Revision History
  6. 6 Device Comparison
    1. 6.1 Related Products
  7. 7 Terminal Configuration and Functions
    1. 7.1 Pin Diagram
    2. 7.2 Signal Descriptions
      1. 7.2.1 Signal Descriptions - Digital
      2. 7.2.2 Signal Descriptions - Analog
    3. 7.3 Pin Attributes
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Power-On Hours (POH)
    4. 8.4  Recommended Operating Conditions
    5. 8.5  Power Supply Specifications
    6. 8.6  Power Consumption Summary
    7. 8.7  RF Specification
    8. 8.8  CPU Specifications
    9. 8.9  Thermal Resistance Characteristics for FCBGA Package [ABL0161]
    10. 8.10 Timing and Switching Characteristics
      1. 8.10.1  Power Supply Sequencing and Reset Timing
      2. 8.10.2  Input Clocks and Oscillators
        1. 8.10.2.1 Clock Specifications
      3. 8.10.3  Multibuffered / Standard Serial Peripheral Interface (MibSPI)
        1. 8.10.3.1 Peripheral Description
        2. 8.10.3.2 MibSPI Transmit and Receive RAM Organization
          1. 8.10.3.2.1 SPI Timing Conditions
          2. 8.10.3.2.2 SPI Master Mode Switching Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input) (1) (1) (1)
          3. 8.10.3.2.3 SPI Master Mode Switching Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input) (1) (1) (1)
        3. 8.10.3.3 SPI Slave Mode I/O Timings
          1. 8.10.3.3.1 SPI Slave Mode Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output) (1) (1) (1)
        4. 8.10.3.4 Typical Interface Protocol Diagram (Slave Mode)
      4. 8.10.4  LVDS Interface Configuration
        1. 8.10.4.1 LVDS Interface Timings
      5. 8.10.5  General-Purpose Input/Output
        1. 8.10.5.1 Switching Characteristics for Output Timing versus Load Capacitance (CL) (1) (1)
      6. 8.10.6  Controller Area Network - Flexible Data-rate (CAN-FD)
        1. 8.10.6.1 Dynamic Characteristics for the CANx TX and RX Pins
      7. 8.10.7  Serial Communication Interface (SCI)
        1. 8.10.7.1 SCI Timing Requirements
      8. 8.10.8  Inter-Integrated Circuit Interface (I2C)
        1. 8.10.8.1 I2C Timing Requirements (1)
      9. 8.10.9  Quad Serial Peripheral Interface (QSPI)
        1. 8.10.9.1 QSPI Timing Conditions
        2. 8.10.9.2 Timing Requirements for QSPI Input (Read) Timings (1) (1)
        3. 8.10.9.3 QSPI Switching Characteristics
      10. 8.10.10 ETM Trace Interface
        1. 8.10.10.1 ETMTRACE Timing Conditions
        2. 8.10.10.2 ETM TRACE Switching Characteristics
      11. 8.10.11 Data Modification Module (DMM)
        1. 8.10.11.1 DMM Timing Requirements
      12. 8.10.12 JTAG Interface
        1. 8.10.12.1 JTAG Timing Conditions
        2. 8.10.12.2 Timing Requirements for IEEE 1149.1 JTAG
        3. 8.10.12.3 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Subsystems
      1. 9.3.1 RF and Analog Subsystem
        1. 9.3.1.1 Clock Subsystem
        2. 9.3.1.2 Transmit Subsystem
        3. 9.3.1.3 Receive Subsystem
      2. 9.3.2 Processor Subsystem
      3. 9.3.3 Host Interface
      4. 9.3.4 Main Subsystem Cortex-R4F
      5. 9.3.5 DSP Subsystem
      6. 9.3.6 Hardware Accelerator
    4. 9.4 Other Subsystems
      1. 9.4.1 ADC Channels (Service) for User Application
        1. 9.4.1.1 GP-ADC Parameter
  10. 10Monitoring and Diagnostics
    1. 10.1 Monitoring and Diagnostic Mechanisms
      1. 10.1.1 Error Signaling Module
  11. 11Applications, Implementation, and Layout
    1. 11.1 Application Information
    2. 11.2 Reference Schematic
  12. 12Device and Documentation Support
    1. 12.1 Device Nomenclature
    2. 12.2 Tools and Software
    3. 12.3 Documentation Support
    4. 12.4 支持资源
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 术语表
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Packaging Information
    2. 13.2 Tray Information for ABL, 10.4 × 10.4 mm

7.2.2 Signal Descriptions - Analog

INTERFACESIGNAL NAMEPIN TYPEDESCRIPTIONBALL NO.
TransmittersTX1OSingle ended transmitter1 o/pB4
TX2OSingle ended transmitter2 o/pB6
TX3OSingle ended transmitter3 o/pB8
ReceiversRX1ISingle ended receiver1 i/pM2
RX2ISingle ended receiver2 i/pK2
RX3ISingle ended receiver3 i/pH2
RX4ISingle ended receiver4 i/pF2
ResetNRESETIPower on reset for chip. Active lowR3
Reference OscillatorCLKPIIn XTAL mode: Differential port for reference crystal
In External clock mode: Single ended input reference clock port		B15
CLKMIIn XTAL mode: Differential port for reference crystal
In External clock mode: Connect this port to ground		C15
Reference clockOSC_CLKOUTOReference clock output from clocking subsystem after cleanup PLL (1.4V output voltage swing).A14
Bandgap voltageVBGAPODevice's Band Gap Reference OutputB10
Power supplyVDDINPower1.2V digital power supplyH15, N11, P15, R6
VIN_SRAMPower1.2V power rail for internal SRAMG15
VNWAPower1.2V power rail for SRAM array back biasP14
VIOINPowerI/O Supply (3.3V or 1.8V): All CMOS I/Os would operate on this supplyR10, F15
VIOIN_18Power1.8V supply for CMOS IOR9
VIN_18CLKPower1.8V supply for clock moduleB11
VIOIN_18DIFFPower1.8V supply for LVDS portD15
VPPPowerVoltage supply for fuse chainL13
Power supplyVIN_13RF1Power1.3V Analog and RF supply,VIN_13RF1 and VIN_13RF2 could be shorted on the boardG5, H5, J5
VIN_13RF2Power1.3V Analog and RF supplyC2,D2
VIN_18BBPower1.8V Analog base band power supplyK5, F5
VIN_18VCOPower1.8V RF VCO supplyB12
VSSGroundDigital groundL5, L6, L8, L10, K7, K8, K9, K10, K11, J6, J7, J8, J10, H7, H9, H11, G6, G7, G8, G10, F9, F11, E5, E6, E8, E10, E11, R15
VSSAGroundAnalog groundA1, A3, A5, A7, A9, A13, A15, B1, B3, B5, B7, B9, B14, C1, C3, C4, C5, C6, C7, C8, C9, C14, E1, E2, E3, F3, G1, G2, G3, H3, J1, J2, J3, K3, L1, L2, L3, M3, N1, N2, N3, R1
Internal LDO output/inputsVOUT_14APLLOInternal LDO outputA10
VOUT_14SYNTHOInternal LDO outputB13
VOUT_PAIOInternal LDO output.
When internal PA LDO is used, this pin provides the output voltage of the LDO. When the internal PA LDO is bypassed, and disabled, the 1-V supply should be fed on this pin. This is mandatory in the 3TX simultaneous use case.		A2, B2
Test and Debug output for pre-production phase. Can be pinned out on production hardware for field debugAnalog Test1 / GPADC1IOAnalog IO dedicated for ADC serviceP1
Analog Test2 / GPADC2IOAnalog IO dedicated for ADC serviceP2
Analog Test3 / GPADC3IOAnalog IO dedicated for ADC serviceP3
Analog Test4 / GPADC4IOAnalog IO dedicated for ADC serviceR2
ANAMUX / GPADC5IOAnalog IO dedicated for ADC serviceC13
VSENSE / GPADC6IOAnalog IO dedicated for ADC serviceD14
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