ZHCSJ06B November 2017 – September 2022 ADS7142-Q1
PRODUCTION DATA
Figure 7-1 shows a small-signal equivalent circuit for the analog input pins. The device includes a two-channel analog multiplexer with each input pin having ESD protection diodes to AVDD and GND. The sampling switches are represented by ideal switches SW1 and SW2 in series with resistors Rs1 and Rs2 (typically 150 Ω). The sampling capacitors, Cs1 and Cs2, are typically 15 pF. The multiplexer configuration is set by the CH_INPUT_CFG register.
During acquisition, switches SW1 and SW2 are closed to allow the input signal to charge the internal sampling capacitors.
During conversion, switches SW1 and SW2 are opened to disconnect the input signal from the sampling capacitors.
The analog inputs of the device are optimized to be driven by a high-impedance source (up to 100 kΩ) in autonomous modes or in high precision mode with a low-power oscillator. When using the high-speed oscillator, drive the analog inputs of the ADC with an external amplifier in autonomous modes or in high precision mode. Figure 6-29 and Figure 6-30 provide the analog input current for CH0 and CH1 of the device.
Figure 7-2, Figure 7-3, and Figure 7-4 provide a simplified circuit for analog input for input configurations described in the Section 7.3.1.1, Section 7.3.1.2, and Section 7.3.1.3 sections, respectively. The analog multiplexer supports following input configurations (set by writing into the CH_INPUT_CFG register).