ZHCSJ06B November   2017  – September 2022 ADS7142-Q1

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: All Modes
    6. 6.6  Electrical Characteristics: Manual Mode
    7. 6.7  Electrical Characteristics: Autonomous Modes
    8. 6.8  Electrical Characteristics: High Precision Mode
    9. 6.9  Timing Requirements
    10. 6.10 Switching Characteristics
    11. 6.11 Timing Diagrams
    12. 6.12 Typical Characteristics: All Modes
    13. 6.13 Typical Characteristics: Manual Mode
    14. 6.14 Typical Characteristics: Autonomous Modes
    15. 6.15 Typical Characteristics: High-Precision Mode
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Analog Input and Multiplexer
        1. 7.3.1.1 Two-Channel, Single-Ended Configuration
        2. 7.3.1.2 Single-Channel, Single-Ended Configuration With Remote Ground Sense
        3. 7.3.1.3 Single-Channel, Pseudo-Differential Configuration
      2. 7.3.2  Offset Calibration
      3. 7.3.3  Reference
      4. 7.3.4  ADC Transfer Function
      5. 7.3.5  Oscillator and Timing Control
      6. 7.3.6  I2C Address Selector
      7. 7.3.7  Data Buffer
        1. 7.3.7.1 Filling of the Data Buffer
        2. 7.3.7.2 Reading Data From the Data Buffer
      8. 7.3.8  Accumulator
      9. 7.3.9  Digital Window Comparator
      10. 7.3.10 I2C Protocol Features
        1. 7.3.10.1 General Call
        2. 7.3.10.2 General Call With Software Reset
        3. 7.3.10.3 General Call With Write Software Programmable Part of the Target Address
        4. 7.3.10.4 Configuring the ADC Into High-Speed I2C Mode
        5. 7.3.10.5 Bus Clear
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Power Up and Reset
      2. 7.4.2 Manual Mode
        1. 7.4.2.1 Manual Mode With CH0 Only
        2. 7.4.2.2 Manual Mode With AUTO Sequence
      3. 7.4.3 Autonomous Modes
        1. 7.4.3.1 Autonomous Mode With Threshold Monitoring and Diagnostics
          1. 7.4.3.1.1 Autonomous Mode With Pre-ALERT Data
          2. 7.4.3.1.2 Autonomous Mode With Post-ALERT Data
        2. 7.4.3.2 Autonomous Mode With Burst Data
          1. 7.4.3.2.1 Autonomous Mode With Start Burst
          2. 7.4.3.2.2 Autonomous Mode With Stop Burst
      4. 7.4.4 High-Precision Mode
    5. 7.5 Programming
      1. 7.5.1 Reading Registers
        1. 7.5.1.1 Single Register Read
        2. 7.5.1.2 Reading a Continuous Block of Registers
      2. 7.5.2 Writing Registers
        1. 7.5.2.1 Single Register Write
        2. 7.5.2.2 Writing a Continuous Block of Registers
        3. 7.5.2.3 Set Bit
        4. 7.5.2.4 Clear Bit
    6. 7.6 Register Map
      1. 7.6.1 Page1 Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 ADS7142-Q1 as a Programmable Comparator With False Trigger Prevention and Diagnostics
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Programmable Thresholds and Hysteresis
          2. 8.2.1.2.2 False Trigger Prevention With an Event Counter
          3. 8.2.1.2.3 Fault Diagnostics With the Data Buffer
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Voltage and Temperature Monitoring in Remote Camera Modules Using the ADS7142-Q1
        1. 8.2.2.1 Design Requirements
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 AVDD and DVDD Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Electrostatic Discharge Caution
    2. 9.2 术语表
    3. 9.3 Trademarks
    4. 9.4 接收文档更新通知
    5. 9.5 支持资源
  10. 10Mechanical, Packaging, and Orderable Information

6.9 Timing Requirements

at TA = -40°C to 125°C, AVDD = 3 V, DVDD = 1.65 V to 3.6 V, All Channel Configurations (unless otherwise noted)(1)
PARAMETER MIN MAX UNIT
STANDARD MODE (100 kHz)
fSCL SCL clock frequency 0 100 kHz
tHD-STA Hold time (repeated) START condition 4 µs
tLOW Low period of SCL 4.7 µs
tHIGH High period of SCL 4 µs
tSU-STA Setup time for a repeated start condition 4.7 µs
tHD-DAT(2)(3) Data hold time 0 µs
tSU-DAT Data setup time 250 ns
tSU-STO Data setup time 4 µs
tBUF Bus free time between a STOP and START condition 4.7 µs
Cb Capacitive load on each line 400 pF
FAST MODE (400 kHz)
fSCL SCL clock frequency 0 400 kHz
tHD-STA Hold time (repeated) START condition 0.6 µs
tLOW Low period of SCL 1.3 µs
tHIGH High period of SCL 0.6 µs
tSU-STA Setup time for a repeated start condition 0.6 µs
tHD-DAT Data hold time 0 µs
tSU-DAT Data setup time 100 ns
tSU-STO Data setup time 0.6 µs
tBUF Bus free time between a STOP and START condition 1.3 µs
Cb Capacitive load on each line 400 pF
FAST MODE PLUS (1000 kHz)
fSCL SCL clock frequency 0 1000 kHz
tHD-STA Hold time (repeated) START condition 0.26 µs
tLOW Low period of SCL 0.5 µs
tHIGH High period of SCL 0.26 µs
tSU-STA Setup time for a repeated start condition 0.26 µs
tHD-DAT Data hold time 0 µs
tSU-DAT Data setup time 50 ns
tSU-STO Data setup time 0.26 µs
tBUF Bus free time between a STOP and START condition 0.5 µs
Cb Capacitive load on each line 550 pF
HIGH SPEED MODE (1.7 MHz, Cb = 400 pF max)
fSCLH SCLH clock frequency 0 1.7 MHz
tHD-STA Hold time (repeated) START condition 160 ns
tLOW Low period of SCL 320 ns
tHIGH High period of SCL 120 ns
tSU-STA Setup time for a repeated start condition 160 ns
tHD-DAT Data hold time 0 150 ns
tSU-DAT Data setup time 10 ns
tSU-STO Data setup time 160 ns
Cb Capacitive load on each line 100 pF
HIGH SPEED MODE (3.4 MHz, Cb = 100 pF max)
fSCLH SCLH clock frequency 0 3.4 MHz
tHD-STA Hold time (repeated) START condition 160 ns
tLOW Low period of SCL 160 ns
tHIGH High period of SCL 60 ns
tSU-STA Setup time for a repeated start condition 160 ns
tHD-DAT Data hold time 0 70 ns
tSU-DAT Data setup time 10 ns
tSU-STO Data setup time 160 ns
Cb Capacitive load on each line 100 pF
(1) All values referred to VIH(min) (0.7 DVDD) and VIL(max) (0.3 DVDD).
(2) tHD-DAT is the data hold time that is measured from the falling edge of SCL and applies to data in transmission and the acknowledge.
(3) The maximum tHD-DAT can be 3.45 µs and 0.9 µs for standard-mode and fast-mode, but must be less than the maximum of tVD-DAT or tVD-ACK by a transition time. This maximum must only be met if the device does not stretch the LOW period  (tLOW) of the SCL signal. If the clock is streched, the data must be valid by the setup time before being released.
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