8.3.1 VDD, VCCI, and Under Voltage Lock Out (UVLO)

The UCC20225 has an internal under voltage lock out (UVLO) protection feature on the supply circuit blocks between the VDD and VSS pins for both outputs. When the VDD bias voltage is lower than V_{VDD_ON} at device start-up or lower than V_{VDD_OFF} after start-up, the VDD UVLO feature holds the effected outputs low, regardless of the status of the input pin (PWM).

When the output stages of the driver are in an unbiased or UVLO condition, the driver outputs are held low by an active clamp circuit that limits the voltage rise on the driver outputs (illustrated in Figure 33 ). In this condition, the upper PMOS is resistively held off by R_Hi-Z while the lower NMOS gate is tied to the driver output through R_CLAMP. In this configuration, the output is effectively clamped to the threshold voltage of the lower NMOS device, typically around 1.5V, when no bias power is available. The clamp sinking current is limited only by the per-channel safety supply power, the ambient temperature, and the 6A peak sink current rating.

Figure 33. Simplified Representation of Active Pull Down Feature

The VDD UVLO protection has a hysteresis feature (V_{VDD_HYS}). This hysteresis prevents chatter when there is ground noise from the power supply. This also allows the device to accept small drops in bias voltage, which occurs when the device starts switching and operating current consumption increases suddenly.

The input side of the UCC20225-Q1 family also has an internal under voltage lock out (UVLO) protection feature. The device isn't active unless the voltage at VCCI exceeds V_{VCCI_ON}. A signal will cease to be delivered when VCCI receives a voltage less than V_{VCCI_OFF}. As with the UVLO for VDD, there is hystersis (V_{VCCI_HYS}) to ensure stable operation.

If PWM is active before VCCI or VDD have crossed above their respective on thresholds, the output will not update until 50µs (typical) after VCCI or VDD crossing its UVLO rising threshold. However, when either VCCI or VDD receive a voltage less than their respective UVLO off thresholds, there is <1µs delay, depending on the voltage slew rate on the supply pins, before the outputs are held low. This asymmetric delay is designed to ensure safe operation during VCCI or VDD brownouts.

The UCC20225-Q1 family can withstand an absolute maximum of 30 V for VDD, and 20 V for VCCI.