9.2.3 Application Curves

Figure 41 and Figure 42 shows the bench test waveforms for the design example shown in Figure 37 under these conditions: VCC = 5 V, VDD = 12 V, f_SW = 200 kHz, V_DC-Link = 400 V.

Channel 1 (Indigo): UCC20225-Q1 family's PWM pin signal.

Channel 2 (Cyan): Gate-source signal on the high side power transistor.

Channel 3 (Magenta): Gate-source signal on the low side power transistor.

In Figure 41, PWM is sent a 3.3 V, 20% duty-cycle signal. The gate drive signals on the power transistor have a 250-ns dead time, shown in the measurement section of Figure 41. The dead time matching is 10-ns with the 250-ns dead time setting. Note that with high voltage present, lower bandwidth differential probes are required, which limits the achievable accuracy of the measurement.

Figure 42 shows a zoomed-in version of the waveform of Figure 41, with measurements for propagation delay and rising/falling time. Importantly, the output waveform is measured between the power transistors’ gate and source pins, and is not measured directly from the driver OUTA and OUTB pins. Due to the split on and off resistors (R_ON, R_OFF), different sink and source currents, and the Miller plateau, different rising (60, 120 ns) and falling time (25 ns) are observed in Figure 42.

Figure 41. Bench Test Waveform for PWM and OUTA/B

Figure 42. Zoomed-In bench-test waveform