7.4.3 SPI Interfaced HART

When interfacing the HART modem via the SPI interface, the device utilizes transmit and receive FIFOs that are 9-bits wide and 16 locations deep to buffer all HART data.

The HART communication protocol is half-duplex protocol which means that either the modulator or demodulator is active, and never simultaneously enabled. The device arbitrates over which component of the modem is active at all times based on activity on the HART bus. Bus activity is interfaced to the host controller through the IRQ pin and MODEM STATUS register.

By default the demodulator is active and the modulator is inactive. When a valid carrier is detected and data is being received by the modem, the CD bit (bit 1) in the MODEM STATUS register is set high. If the CD bit (bit 1) in the MODEM IRQ MASK register is set to 0, this will also cause the IRQ pin to toggle as programmed in the status CONTROL register. The IRQ pin may be programmed to be edge sensitive or level sensitive, the polarity of the signal is also programmable. When the IRQ pin toggles, the MODEM STATUS register should be read to determine the source of the interrupt. Receive data can be read from the RECEIVE FIFO by issuing an SPI read command.

Alternatively, the CD pin can be ignored by setting the CD bit (bit 1) in the MODEM IRQ MASK register to a 1. In this mode the IRQ pin will not toggle when the CD bit in the MODEM STATUS register is a 1. Instead, a RECEIVE FIFO read event can be triggered by the RECEIVE FIFO level threshold. This is achieved by programming the FIFO LEVEL SET register (bits 7:4) to the desired threshold value from 1-15, if a full FIFO (level 16 threshold) is desired the M2D FIFO FULL alarm can be used instead. If the M2D FIFO LEVEL bit (bit 7) in the MODEM IRQ MASK register is set to 0, the IRQ pin will toggle and the MODEM STATUS register should be read to determine the source of the interrupt. Receive data can then be read from the RECEIVE FIFO by issuing an SPI read command.

If data is placed in the transmit FIFO while the demodulator is active and the CD bit is high, the data remains in the FIFO until the modulator is activated. To request that the modulator is activated and the demodulator is deactivated the RTS bit (bit 0) in the MODEM CONTROL register should be set high. When the modulator is activated and the demodulator is deactivated the clear to send, or CTS, bit (bit 0) in the MODEM STATUS register is set high. If the CTS bit (bit 0) in the MODEM IRQ MASK register is set to a 0 this will cause the IRQ pin to toggle, indicating that transmit FIFO data will begin to be placed on the bus.

The level of the transmit FIFO may be monitored in order to avoid buffer overflow. This can be done either by watching for a buffer full or buffer threshold event. To monitor by a FIFO level threshold the FIFO LEVEL SET register (bits 3:0) can be programmed to the desired threshold value from 1-15. If the D2M FIFO LEVEL bit (bit 4) in the MODEM IRQ MASK register is set to a 0, this will cause the IRQ pin to toggle. Similarly an alarm can be triggered based on the D2M FIFO FULL bit in the MODEM STATUS register.