ZHCSJ40 December   2018 DAC8742H

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      简化原理图
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  HART Modulator
      2. 7.3.2  HART Demodulator
      3. 7.3.3  FOUNDATION FIELDBUS / PROFIBUS PA Manchester Encoder
      4. 7.3.4  FOUNDATION FIELDBUS / PROFIBUS PA Manchester Decoder
      5. 7.3.5  Internal Reference
      6. 7.3.6  Clock Configuration
      7. 7.3.7  Reset and Power-Down
      8. 7.3.8  Full-Duplex Mode
      9. 7.3.9  I/O Selection
      10. 7.3.10 Jabber Inhibitor
    4. 7.4 Device Functional Modes
      1. 7.4.1 UART Interfaced HART
      2. 7.4.2 UART Interfaced FOUNDATION FIELDBUS / PROFIBUS PA
      3. 7.4.3 SPI Interfaced HART
      4. 7.4.4 SPI Interfaced FOUNDATION FIELDBUS / PROFIBUS PA
      5. 7.4.5 Interface
        1. 7.4.5.1 UART
          1. 7.4.5.1.1 UART Carrier Detect
        2. 7.4.5.2 SPI
          1. 7.4.5.2.1 SPI Cyclic Redundancy Check
          2. 7.4.5.2.2 SPI Interrupt Request
    5. 7.5 Register Maps
      1. 7.5.1 CONTROL Register (Offset = 2h) [reset = 0x8042]
        1. Table 4. CONTROL Register Field Descriptions
      2. 7.5.2 RESET Register (Offset = 7h) [reset = 0x0000]
        1. Table 5. RESET Register Field Descriptions
      3. 7.5.3 MODEM_STATUS Register (Offset = 20h) [reset = 0x0000]
        1. Table 6. MODEM_STATUS Register Field Descriptions
      4. 7.5.4 MODEM_IRQ_MASK Register (Offset = 21h) [reset = 0x0024]
        1. Table 7. MODEM_IRQ_MASK Register Field Descriptions
      5. 7.5.5 MODEM_CONTROL Register (Offset = 22h) [reset = 0x0048]
        1. Table 8. MODEM_CONTROL Register Field Descriptions
      6. 7.5.6 FIFO_D2M Register (Offset = 23h) [reset = 0x0200]
        1. Table 9. FIFO_D2M Register Field Descriptions
      7. 7.5.7 FIFO_M2D Register (Offset = 24h) [reset = 0x0200]
        1. Table 10. FIFO_M2D Register Field Descriptions
      8. 7.5.8 FIFO_LEVEL_SET Register (Offset = 25h) [reset = 0x0000]
        1. Table 11. FIFO_LEVEL_SET Register Field Descriptions
      9. 7.5.9 PAFF_JABBER Register (Offset = 27h) [reset = 0x0000]
        1. Table 12. PAFF_JABBER Register Field Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Design Recommendations
      2. 8.1.2 Selecting the Crystal/Resonator
      3. 8.1.3 Included Functions and Filter Selection
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 DAC8742H HART Modem
        2. 8.2.2.2 2-Wire Current Loop
        3. 8.2.2.3 Regulator
        4. 8.2.2.4 DAC
        5. 8.2.2.5 Amplifiers
        6. 8.2.2.6 Diodes
        7. 8.2.2.7 Passives
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 文档支持
      1. 11.1.1 相关文档
    2. 11.2 接收文档更新通知
    3. 11.3 社区资源
    4. 11.4 商标
    5. 11.5 静电放电警告
    6. 11.6 术语表
  12. 12机械、封装和可订购信息

8.2.2.5 Amplifiers

Next, the voltage output is buffered with the OPA333 CMOS operation amplifier, which features near-zero drift over time and temperature, low quiescent current (17 µA), and single supply operation with rail-to-rail output that swings within 50 mV of the supply rail.

As with the OPA333, the OPA335 was chosen due to its excellent DC accuracy specifications. These parameters include low input bias current, low offset voltage, and high CMRR/PSRR. In addition to these DC specifications, the OPA335 features an operating bandwidth of up to 2 MHz, which provides ample margin for HART communication.

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