The device supports a STANDBY mode of operation where some of the internal circuits of the device are powered down. However, if bit 6 in configuration register is set to 1 (CFR.B6 = 1), then the internal reference is not powered down and the contents of the REFDAC_A and REFDAC_B registers are retained to enable faster power-up to a normal mode of operation.

As shown in Figure 7-8, a valid write operation in frame (F) programs the configuration register with B5 set to 1 (CFR.B5 = 1) and places the device into a STANDBY mode of operation on the following CS rising edge. While in STANDBY mode, SDO_A and SDO_B output all 1s when CS is low and remain in 3-state when CS is high.

To remain in STANDBY mode, SDI must remain low in the subsequent frames.

N is a function of the device configuration, as described in Table 7-4.

Figure 7-8 Enter STANDBY Mode

As shown in Figure 7-9, a valid write operation in frame (F+3) writes the configuration register with B5 set to 0 (CFR.B5 = 0) and brings the device out of STANDBY mode on the following CS rising edge. Frame (F+3) must have at least 48 SCLK falling edges.

After exiting the STANDBY mode, a delay of t_{PU_STDBY} must elapse for the internal circuits to fully power-up and resume normal operation in frame (F+4). Device configuration for frame (F+4) is determined by the status of the CFR.B[11:6] bits programmed during frame (F+3).

N is a function of the device configuration, as described in Table 7-4.

Figure 7-9 Exit STANDBY Mode

See the Section 6.6 table for timing specifications for this operating mode.