ZHCSJ89B January   2019  – July 2022 ADS8353-Q1

PRODUCTION DATA  

  1. 1特性
  2. 2应用
  3. 3说明
  4. 4Revision History
  5. 5Pin Configuration and Functions
  6. 6Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Thermal Information
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Timing Diagram
    9. 6.9 Typical Characteristics
  7. 7Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Reference
      2. 7.3.2 Analog Inputs
        1. 7.3.2.1 Analog Input: Full-Scale Range Selection
        2. 7.3.2.2 Analog Input: Single-Ended and Pseudo-Differential Configurations
      3. 7.3.3 Transfer Function
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
      2. 7.5.2 Write to User-Programmable Registers
      3. 7.5.3 Data Read Operation
        1. 7.5.3.1 Reading User-Programmable Registers
        2. 7.5.3.2 Conversion Data Read
          1. 7.5.3.2.1 32-CLK, Dual-SDO Mode (CFR.B11 = 0, CFR.B10 = 0, Default)
          2. 7.5.3.2.2 32-CLK, Single-SDO Mode (CFR.B11 = 0, CFR.B10 = 1)
      4. 7.5.4 Low-Power Modes
        1. 7.5.4.1 STANDBY Mode
        2. 7.5.4.2 Software Power-Down (SPD) Mode
      5. 7.5.5 Frame Abort, Reconversion, or Short-Cycling
    6. 7.6 Register Maps
      1. 7.6.1 ADS8353-Q1 Registers
  8. 8Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Input Amplifier Selection
      2. 8.1.2 Charge Kickback Filter
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. 9Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 接收文档更新通知
    4. 9.4 支持资源
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 术语表
      1.      Mechanical, Packaging, and Orderable Information

7.5.3.1 Reading User-Programmable Registers

The device supports a readback option for all user-programmable registers: CFR, REFDAC_A, and REFDAC_B. Figure 7-5 shows a detailed timing diagram for this operation.

GUID-0B5DD6F3-C43B-4505-84F4-A3D3C0AF87F1-low.gif
N is a function of the device configuration, as described in Table 7-4.
Figure 7-5 Register Readback Timing

To readback the user-programmable register settings, transmit the appropriate control word, as shown in Table 7-6, to the device during frame (F+1). Frame (F+1) must have at least 48 SCLK falling edges.

Table 7-6 Control Word to Readback User-Programmable Registers
USER-PROGRAMMABLE REGISTER CONTROL WORD TO BE PROGRAMMED IN FRAME (F+1)
B[15:12] (Binary) B[11:0] (Hex)
CFR 0011b 000h
REFDAC_A 0001b 000h
REFDAC_B 0010b 000h

Frame (F+2) must have at least 48 SCLK falling edges. During frame (F+2), SDO_A outputs the contents of the selected user-programmable register on the first 16 SCLK falling edges (as shown in Table 7-7) and then outputs 0's for any subsequent SCLK falling edges. The SDO_B pin outputs 0's for all SCLK falling edges.

Table 7-7 Register Data Read Back
USER-PROGRAMMABLE REGISTER DATA READ ON SDO-A IN FRAME (F+2)
R15 R14 R13 R12 R11 — R3 R2 R1 R0
CFR 0 0 1 1 CFG.B11 — CFG.B3 CFG.B2 CFG.B1 CFG.B0
REFDAC_A 0 0 0 1 REFDAC_A.D8 — REFDAC_A.D0 0 0 0
REFDAC_B 0 0 1 0 REFDAC_B.D8 — REFDAC_B.D0 0 0 0

Register settings programmed during frame (F+2) determine the device configuration in frame (F+3).
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