In TDM/I2S Mode, the device operates from SBCLK. Table 7-95 and Table 7-96 below shows the valid SBCLK frequencies for each sample rate and SBCLK to FSYNC ratio (for 44.1 kHz and 48 kHz family frequencies respectively.
If the sample rate is properly configured via the SAMP_RATE[1:0] bits, no additional configuration is required as long as the SBCLK to FSYNC ratio is valid. The device will detect improper SBCLK frequencies and SBCLK to FSYNC ratios and volume ramp down the playback path to minimize audible artifacts. After the clock error is detected the device will enter a low power halt mode after CLK_HALT_TIMER if CLK_HALT_EN is enabled. Additionally the device can automatically power up and down on valid clock signals if CLK_ERR_PWR_EN is set. The device sampling rate should not be changed while this feature is enabled. Additionally, the CLK_HALT_EN should be set when CLK_ERR_PWR_EN is set for this feature to work properly.
Table 7-95 Supported SBCLK Frequencies (48 kHz based sample rates)| Sample Rate (kHz) | SBCLK to FSYNC Ratio |
|---|
| 64 | 96 | 128 | 192 | 256 | 384 | 512 |
|---|
| 16 kHz | 1.024 MHz | 1.536 MHz | 2.048 MHz | 3.072 MHz | 4.096 MHz | 6.144 MHz | 8.192 MHz |
| 32 kHz | 2.048 MHz | 3.072 MHz | 4.0960 MHz | 6.144 MHz | 8.192 MHz | 12.288 MHz | 16.384 MHz |
| 48 kHz | 3.072 MHz | 4.608 MHz | 6.144 MHz | 9.216 MHz | 12.288 MHz | 18.432 MHz | 24.576 MHz |
| 96 kHz | 6.144 MHz | 9.216 MHz | 12.288 MHz | 18.432 MHz | 24.576 MHz | - | - |
Table 7-96 Supported SBCLK Frequencies (44.1 kHz based sample rates)| Sample Rate (kHz) | SBCLK to FSYNC Ratio |
|---|
| 64 | 96 | 128 | 192 | 256 | 384 | 512 |
|---|
| 14.7 kHz | 940.8 kHz | 1.4112 MHz | 1.8816 MHz | 2.8224 MHz | 3.7632 MHz | 5.6448 MHz | 7.5264 MHz |
| 29.4 kHz | 1.8816 MHz | 2.8224 MHz | 3.7632 MHz | 5.6448 MHz | 7.5264 MHz | 11.2896 MHz | 15.0528 MHz |
| 44.1 kHz | 2.8224 MHz | 4.2336 MHz | 5.6448 MHz | 8.4672 MHz | 11.2896 MHz | 16.9344 MHz | 22.5792 MHz |
| 88.2 kHz | 5.6448 MHz | 8.4672 MHz | 11.2896 MHz | 16.9344 MHz | 22.5792 MHz | - | - |
Table 7-97 Clock Power Up/Down on Valid ASI Clocks| CLK_ERR_PWR_EN | Setting |
|---|
0
| Disabled (default) |
1
| Enabled |
Table 7-98 Clock Halt(Sleep) After Errors Longer Than Halt Timer| CLK_HALT_EN | Setting |
|---|
0
| Enabled (default) |
1
| Disabled |
Table 7-99 Clock Halt Timer| CLK_HALT_TIMER[2:0] | Setting |
|---|
000
| 1 ms |
001
| 3.27 ms |
010
| 26.21 ms |
011
| 52.42 ms (default) |
100
| 104.85 ms |
101
| 209.71 ms |
110
| 419.43 ms |
111
| 838.86 ms |