ZHCSJB4D April   2019  – January 2024 TAS2563

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  I2C Timing Requirements
    7. 5.7  SPI Timing Requirements
    8. 5.8  PDM Port Timing Requirements
    9. 5.9  TDM Port Timing Requirements
    10. 5.10 Timing Diagrams
    11. 5.11 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  PurePath Console 3 Software
      2. 7.3.2  Device Mode and Address Selection
      3. 7.3.3  General I2C Operation
      4. 7.3.4  General SPI Operation
      5. 7.3.5  Single-Byte and Multiple-Byte Transfers
      6. 7.3.6  Single-Byte Write
      7. 7.3.7  Multiple-Byte Write and Incremental Multiple-Byte Write
      8. 7.3.8  Single-Byte Read
      9. 7.3.9  Multiple-Byte Read
      10. 7.3.10 Register Organization
      11. 7.3.11 Operational Modes
        1. 7.3.11.1 Hardware Shutdown
        2. 7.3.11.2 Software Shutdown
        3. 7.3.11.3 Mute
        4. 7.3.11.4 Active
        5. 7.3.11.5 Perform Load Diagnostics
        6. 7.3.11.6 Mode Control and Software Reset
      12. 7.3.12 Faults and Status
      13. 7.3.13 Digital Input Pull Downs
    4. 7.4 Device Functional Modes
      1. 7.4.1 PDM Input
      2. 7.4.2 TDM Port
      3. 7.4.3 Playback Signal Path
        1. 7.4.3.1 Digital Signal Processor
        2. 7.4.3.2 High Pass Filter
        3. 7.4.3.3 Digital Volume Control and Amplifier Output Level
        4. 7.4.3.4 Auto-mute During Idle Channel Mode
        5. 7.4.3.5 Auto-start/stop on Audio Clocks
        6. 7.4.3.6 Supply Tracking Limiters with Brown Out Prevention
        7. 7.4.3.7 Class-D Settings
      4. 7.4.4 SAR ADC
      5. 7.4.5 Boost
      6. 7.4.6 IV Sense
      7. 7.4.7 Load Diagnostics
      8. 7.4.8 Clocks and PLL
      9. 7.4.9 Thermal Foldback
    5. 7.5 Register Maps
      1. 7.5.1  Register Summary Table Page=0x00
      2. 7.5.2  PAGE (page=0x00 address=0x00) [reset=0h]
      3. 7.5.3  SW_RESET (page=0x00 address=0x01) [reset=0h]
      4. 7.5.4  PWR_CTL (page=0x00 address=0x02) [reset=Eh]
      5. 7.5.5  PB_CFG1 (page=0x00 address=0x03) [reset=20h]
      6. 7.5.6  MISC_CFG1 (page=0x00 address=0x04) [reset=C6h]
      7. 7.5.7  MISC_CFG2 (page=0x00 address=0x05) [reset=22h]
      8. 7.5.8  TDM_CFG0 (page=0x00 address=0x06) [reset=9h]
      9. 7.5.9  TDM_CFG1 (page=0x00 address=0x07) [reset=2h]
      10. 7.5.10 TDM_CFG2 (page=0x00 address=0x08) [reset=4Ah]
      11. 7.5.11 TDM_CFG3 (page=0x00 address=0x09) [reset=10h]
      12. 7.5.12 TDM_CFG4 (page=0x00 address=0x0A) [reset=13h]
      13. 7.5.13 TDM_CFG5 (page=0x00 address=0x0B) [reset=2h]
      14. 7.5.14 TDM_CFG6 (page=0x00 address=0x0C) [reset=0h]
      15. 7.5.15 TDM_CFG7 (page=0x00 address=0x0D) [reset=4h]
      16. 7.5.16 TDM_CFG8 (page=0x00 address=0x0E) [reset=5h]
      17. 7.5.17 TDM_CFG9 (page=0x00 address=0x0F) [reset=6h]
      18. 7.5.18 TDM_CFG10 (page=0x00 address=0x10) [reset=7h]
      19. 7.5.19 DSP Mode & TDM_DET (page=0x00 address=0x11) [reset=7Fh]
      20. 7.5.20 LIM_CFG0 (page=0x00 address=0x12) [reset=12h]
      21. 7.5.21 LIM_CFG1 (page=0x00 address=0x13) [reset=76h]
      22. 7.5.22 DSP FREQUENCY & BOP_CFG0 (page=0x00 address=0x14) [reset=1h]
      23. 7.5.23 BOP_CFG0 (page=0x00 address=0x15) [reset=2Eh]
      24. 7.5.24 BIL_and_ICLA_CFG0 (page=0x00 address=0x16) [reset=60h]
      25. 7.5.25 BIL_ICLA_CFG1 (page=0x00 address=0x17) [reset=0h]
      26. 7.5.26 GAIN_ICLA_CFG0 (page=0x00 address=0x18) [reset=0h]
      27. 7.5.27 ICLA_CFG1 (page=0x00 address=0x19) [reset=0h]
      28. 7.5.28 INT_MASK0 (page=0x00 address=0x1A) [reset=FCh]
      29. 7.5.29 INT_MASK1 (page=0x00 address=0x1B) [reset=A6h]
      30. 7.5.30 INT_MASK2 (page=0x00 address=0x1C) [reset=DFh]
      31. 7.5.31 INT_MASK3 (page=0x00 address=0x1D) [reset=FFh]
      32. 7.5.32 INT_LIVE0 (page=0x00 address=0x1F) [reset=0h]
      33. 7.5.33 INT_LIVE1 (page=0x00 address=0x20) [reset=0h]
      34. 7.5.34 INT_LIVE3 (page=0x00 address=0x21) [reset=0h]
      35. 7.5.35 INT_LIVE4 (page=0x00 address=0x22) [reset=0h]
      36. 7.5.36 INT_LTCH0 (page=0x00 address=0x24) [reset=0h]
      37. 7.5.37 INT_LTCH1 (page=0x00 address=0x25) [reset=0h]
      38. 7.5.38 INT_LTCH3 (page=0x00 address=0x26) [reset=0h]
      39. 7.5.39 INT_LTCH4 (page=0x00 address=0x27) [reset=0h]
      40. 7.5.40 VBAT_MSB (page=0x00 address=0x2A) [reset=0h]
      41. 7.5.41 VBAT_LSB (page=0x00 address=0x2B) [reset=0h]
      42. 7.5.42 TEMP (page=0x00 address=0x2C) [reset=0h]
      43. 7.5.43 INT & CLK CFG (page=0x00 address=0x30) [reset=19h]
      44. 7.5.44 DIN_PD (page=0x00 address=0x31) [reset=40h]
      45. 7.5.45 MISC (page=0x00 address=0x32) [reset=80h]
      46. 7.5.46 BOOST_CFG1 (page=0x00 address=0x33) [reset=34h]
      47. 7.5.47 BOOST_CFG2 (page=0x00 address=0x34) [reset=4Bh]
      48. 7.5.48 BOOST_CFG3 (page=0x00 address=0x35) [reset=74h]
      49. 7.5.49 MISC (page=0x00 address=0x3B) [reset=58h]
      50. 7.5.50 TG_CFG0 (page=0x00 address=0x3F) [reset=0h]
      51. 7.5.51 BST_ILIM_CFG0 (page=0x00 address=0x40) [reset=36h]
      52. 7.5.52 PDM_CONFIG0 (page=0x00 address=0x41) [reset=1h]
      53. 7.5.53 DIN_PD & PDM_CONFIG3 (page=0x00 address=0x42) [reset=F8h]
      54. 7.5.54 ASI2_CONFIG0 (page=0x00 address=0x43) [reset=8h]
      55. 7.5.55 ASI2_CONFIG1 (page=0x00 address=0x44) [reset=0h]
      56. 7.5.56 ASI2_CONFIG2 (page=0x00 address=0x45) [reset=1h]
      57. 7.5.57 ASI2_CONFIG3 (page=0x00 address=0x46) [reset=FCh]
      58. 7.5.58 PVDD_MSB_DSP (page=0x00 address=0x49) [reset=0h]
      59. 7.5.59 PVDD_LSB_DSP (page=0x00 address=0x4A) [reset=0h]
      60. 7.5.60 REV_ID (page=0x00 address=0x7D) [reset=0h]
      61. 7.5.61 I2C_CKSUM (page=0x00 address=0x7E) [reset=0h]
      62. 7.5.62 BOOK (page=0x00 address=0x7F) [reset=0h]
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Mono/Stereo Configuration
        2. 8.2.2.2 Boost Converter Passive Devices
        3. 8.2.2.3 EMI Passive Devices
        4. 8.2.2.4 Miscellaneous Passive Devices
      3. 8.2.3 Application Curves
  10. 9 Power Supply Recommendations
    1. 9.1 Power Supplies
    2. 9.2 Power Supply Sequencing
      1. 9.2.1 Boost Supply Details
      2. 9.2.2 External Boost Mode (Boost Bypass Mode)
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 支持资源
    4. 11.4 Trademarks
    5. 11.5 静电放电警告
    6. 11.6 术语表
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

7.4.2 TDM Port

The TAS2563 provides a flexible TDM serial audio port. The port can be configured to support a variety of formats including stereo I2S, Left Justified and TDM. Mono audio playback is available via the SDIN pin. The SDOUT pin is used to transmit sample streams including speaker voltage and current sense, VBAT voltage, die temperature and channel gain.

The TDM serial audio port supports up to 16 32-bit time slots at 44.1/48 kHz, 8 32-bit time slots at a 88.2/96 kHz sample rate and 4 32-bit time slots at a 176.4/192 kHz sample rate. The device supports 2 time slots at 32 bits in width and 4 or 8 time slots at 16, 24 or 32 bits in width. Valid SBCLK to FSYNC ratios are 64, 96, 128, 192, 256, 384 and 512. The device will automatically detect the number of time slots and this does not need to be programmed.

By default, the TAS2563 will automatically detect the PCM playback sample rate. This can be disabled by setting the AUTO_RATE register bit high and manually configuring the device.

The SAMP_RATE[2:0] register bits set the PCM audio sample rate when AUTO_RATE is enabled. The TAS2563 employs a robust clock fault detection engine that will automatically volume ramp down the playback path if FSYNC does not match the configured sample rate (AUTO_RATE enabled) or the ratio of SBCLK to FSYNC is not supported (minimizing any audible artifacts). Once the clocks are detected to be valid in both frequency and ratio, the device will automatically volume ramp the playback path back to the configured volume and resume playback.

When using the auto rate detection the sampling rate and SBCLK to FSYNC ratio detected on the TDM bus is reported back on the read-only register FS_RATE and FS_RATIO respectively.

While the sampling rate of 192 kHz is supported, it is internally down-sampled to 96 kHz. Therefore audio content greater than 40 kHz should not be applied to prevent aliasing. This additionally affects all processing blocks like BOP and limiter which should use 96 kHz fs when accepting 192 kHz audio. It is recommend to use Section 7.3.1 to configure the device.

Table 7-22 PCM Auto Sample Rate Detection
AUTO_RATE SETTING 
0
 Enabled (default) 
1
 Disabled
Table 7-23 PCM Audio Sample Rates
SAMP_RATE[2:0] FS_RATE(read only) SAMPLE RATE 
000
 
000
 Reserved 
001
 
001
 14.7 kHz / 16 kHz 
010
 
010
 Reserved 
011
 
011
 29.4 kHz / 32 kHz 
100
 
100
 44.1 kHz / 48 kHz (default) 
101
 
101
 88.2 kHz / 96 kHz 
110
 
110
 176.4 kHz / 192 kHz supported only by QFN device package. 
111
 
111
 Reserved
Table 7-24 PCM SBCLK to FSYNC Ratio
FS_RATIO[3:0] SBCLK to FSYNC Ratio 
0x0-0x3
 Reserved 
0x4
 64 
0x5
 96 
0x6
 128 
0x7
 192 
0x8
 256 
0x9
 384 
0xA
 512 
0xB-0xE
 Reserved 
0xF
 Error Condition

Figure 7-12 and Figure 7-13 below illustrates the receiver frame parameters required to configure the port for playback. A frame begins with the transition of FSYNC from either high to low or low to high (set by the FRAME_START register bit). FSYNC and SDIN are sampled by SBCLK using either the rising or falling edge (set by the RX_EDGE register bit). The RX_OFFSET[4:0] register bits define the number of SBCLK cycles from the transition of FSYNC until the beginning of time slot 0. This is typically set to a value of 0 for Left Justified format and 1 for an I2S format.

GUID-C6E7F7B7-9BE6-46DE-8B49-E6A8FC39F694-low.gif Figure 7-12 TDM RX Time Slot with Left Justification
GUID-5BF4B2FA-87C1-48B0-9C75-B5CDB3342E8E-low.gif Figure 7-13 TDM RX Time Slots
Table 7-25 TDM Start of Frame Polarity
FRAME_START POLARITY 
0
 Low to High on FSYNC(1) 
1
 High to Low on FSYNC (default)(2)
(1) When Low to High is used RX_EDGE and TX_EDGE cannot both simultaneously be set to rising edge.
(2) When High to Low is used RX_EDGE and TX_EDGE cannot both simultaneously be set to falling edge.
Table 7-26 TDM RX Capture Polarity
RX_EDGE FSYNC AND SDIN CAPTURE EDGE 
0
 Rising edge of SBCLK (default) 
1
 Falling edge of SBCLK
Table 7-27 TDM RX Start of Frame to Time Slot 0 Offset
RX_OFFSET[4:0] SBCLK CYCLES 
0x00
 0 
0x01
 1 (default) 
0x02
 2 
...
 ... 
0x1E
 30 
0x1F
 31

The RX_SLEN[1:0] register bits set the length of the RX time slot. The length of the audio sample word within the time slot is configured by the RX_WLEN[1:0] register bits. The RX port will left justify the audio sample within the time slot by default, but this can be changed to right justification via the RX_JUSTIFY register bit. The TAS2563 supports mono and stereo down mix playback ([L+R]/2) via the left time slot, right time slot and time slot configuration register bits (RX_SLOT_L[3:0], RX_SLOT_R[3:0] and RX_SCFG[1:0] respectively). By default the device will playback mono from the time slot equal to the I2C base address offset for playback. The RX_SCFG[1:0] register bits can be used to override the playback source to the left time slot, right time slot or stereo down mix set by the RX_SLOT_L[3:0] and RX_SLOT_R[3:0] register bits.

If time slot selections places reception either partially or fully beyond the frame boundary, the receiver will return a null sample equivalent to a digitally muted sample.

Table 7-28 TDM RX Time Slot Length
RX_SLEN[1:0] TIME SLOT LENGTH 
00
 16-bits 
01
 24-bits 
10
 32-bits (default) 
11
 reserved
Table 7-29 TDM RX Sample Word Length
RX_WLEN[1:0] LENGTH 
00
 16-bits 
01
 20-bits 
10
 24-bits (default) 
11
 32-bits
Table 7-30 TDM RX Sample Justification
RX_JUSTIFY JUSTIFICATION 
0
 Left (default) 
1
 Right
Table 7-31 TDM RX Time Slot Select Configuration
RX_SCFG[1:0] CONFIG ORIGIN 
00
 Mono with Time Slot equal to I2C Address Offset (default) 
01
 Mono Left Channel 
10
 Mono Right Channel 
11
 Stereo Down Mix [L+R]/2
Table 7-32 TDM RX Left Channel Time Slot
RX_SLOT_L[3:0] TIME SLOT 
0x0
 0 (default) 
0x1
 1 
...
 ... 
0xE
 14 
0xF
 15
Table 7-33 TDM RX Right Channel Time Slot
RX_SLOT_R[3:0] TIME SLOT 
0x0
 0 
0x1
 1 (default) 
...
 ... 
0xE
 14 
0xF
 15

The TDM port can transmit a number sample streams on the SDOUT pin including speaker voltage sense, speaker current sense, VBAT voltage, die temperature and channel gain. Figure 7-14 below illustrates the alignment of time slots to the beginning of a frame and how a given sample stream is mapped to time slots. Either the rising or falling edge of SBCLK can be used to transmit data on the SDOUT pin, which can be configured by setting the TX_EDGE register bit. The TX_OFFSET register defines the number SBCLK cycles between the start of a frame and the beginning of time slot 0. This would typically be programmed to 0 for Left Justified format and 1 for I2S format. The TDM TX can either transmit logic 0 or Hi-Z depending on the setting of the TX_FILL register bit setting. An optional bus keeper will weakly hold the state of SDOUT when all devices driving are Hi-Z. Since only one bus keeper is required on SDOUT, this feature can be disabled via the TX_KEEPEN register bit. The bus-keeper can additionally be configured to be enabled for only 1LSB cycle or always using TX_KEEPLN and to drive the full or half cycle of the LSB using TX_KEEPCY.

Each sample stream is composed of either one or two 8-bit time slots. , so they will always utilize two TX time slots. The VBAT voltage stream is 10-bit precision, and can either be transmitted left justified in a 16-bit word (using two time slots) or can be truncated to 8-bits (the top 8 MSBs) and be transmitted in a single time slot. This is configured by setting VBAT_SLEN register bit. The Die temperature and gain are both 8-bit precision and are transmitted in a single time slot.

GUID-6B70DBDA-645F-4691-A55F-3FF6CC83DE47-low.gif Figure 7-14 TDM Port TX Diagram
Table 7-34 TDM TX Transmit Polarity
TX_EDGE SDOUT TRANSMIT EDGE 
0
 Rising edge of SBCLK 
1
 Falling edge of SBCLK (default)
Table 7-35 TDM TX Start of Frame to Time Slot 0 Offset
TX_OFFSET[2:0] SBCLK CYCLES 
0x0
 0 
0x1
 1 (default) 
0x2
 2 
...
 ... 
0x6
 6 
0x7
 7
Table 7-36 TDM TX Unused Bit Field Fill
TX_FILL SDOUT UNUSED BIT FIELDS 
0
 Transmit 0 
1
 Transmit Hi-Z (default)
Table 7-37 TDM TX SDOUT Bus Keeper Enable
TX_KEEPEN SDOUT BUS KEEPER 
0
 Disable bus keeper 
1
 Enable bus keeper (default)
Table 7-38 TDM TX SDOUT Bus Keeper Length
TX_KEEPLN SDOUT BUS KEEPER ENABLED FOR 
0
 1 LSB cycle (default) 
1
 Always
Table 7-39 TDM TX SDOUT Bus Keeper LSB Cycle
TX_KEEPCY SDOUT BUS KEEPER DRIVEN 
0
 full-cycle (default) 
1
 half-cycle

The time slot register for each sample stream defines where the MSB transmission begins. For instance, if VSNS_SLOT is set to 2, the upper 8 MSBs will be transmitted in time slot 2 and the lower 8 LSBs will be transmitted in time slot 3. Each sample stream can be individually enabled or disabled. This is useful to manage limited TDM bandwidth since it may not be necessary to transmit all streams for all devices on the bus.

It is important to ensure that time slot assignments for actively transmitted sample streams do not conflict. For instance, if VSNS_SLOT is set to 2 and ISNS_SLOT is set to 3, the lower 8 LSBs of voltage sense will conflict with the upper 8 MSBs of current sense. This will produce unpredictable transmission results in the conflicting bit slots (for example the priority is not defined).

The current and voltage values are transmitted at the full 16-bit measured values by default. The IVMON_LEN register can be used to transmit only the 8 MSB bits in one slot or 12 MSB bits values across multiple slots. The special 12-bit mode is used when only 24-bit I2S/TDM data can be processed by the host processor. The device should be configured with the voltage-sense slot and current-sense slot off by 1 slot and will consume 3 consecutive 8-bit slots. In this mode the device will transmit the first 12 MSB bits followed by the second 12 MSB bits specified by the preceding slot.

If time slot selections place transmission beyond the frame boundary, the transmitter will truncate transmission at the frame boundary.

It is recommended to keep the following slot ordering:               

ISNS_SLOT<VSNS_SLOT<VBAT_SLOT<TEMP_SLOT<GAIN_SLOT<BIL_ILIM_SLOT.

Table 7-40 TDM Voltage/Current Length
IVMON_LEN[1:0] LENGTH BITS 
00
 16 bits (default) 
01
 12 bits 
10
 8 bits 
11
 Reserved
Table 7-41 TDM Voltage Sense Time Slot
VSNS_SLOT[5:0] SLOT 
0x00
 0 
0x01
 1 
0x02
 2 (default) 
...
 ... 
0x3E
 62 
0x3F
 63
Table 7-42 TDM Voltage Sense Transmit Enable
VSNS_TX STATE 
0
 Disabled (default) 
1
 Enabled
Table 7-43 TDM Current Sense Time Slot
ISNS_SLOT[5:0] SLOT 
0x00
 0 (default) 
0x01
 1 
0x02
 2 
...
 ... 
0x3E
 62 
0x3F
 63
Table 7-44 TDM Current Sense Transmit Enable
ISNS_TX STATE 
0
 Disabled (default) 
1
 Enabled
Table 7-45 TDM VBAT Time Slot
VBAT_SLOT[5:0] SLOT 
0x00
 0 
0x01
 1 
...
 ... 
0x04
 4 (default) 
...
 ... 
0x3E
 62 
0x3F
 63
Table 7-46 TDM VBAT Time Slot Length
VBAT_SLEN SLOT LENGTH 
0
 Truncate to 8-bits (default) 
1
 Left justify to 16-bits
Table 7-47 TDM VBAT Transmit Enable
VBAT_TX STATE 
0
 Disabled (default) 
1
 Enabled
Table 7-48 TDM Temp Sensor Time Slot
TEMP_SLOT[5:0] SLOT 
0x00
 0 
0x01
 1 
...
 ... 
0x05
 5 (default) 
...
 ... 
0x3E
 62 
0x3F
 63
Table 7-49 TDM Temp Sensor Transmit Enable
TEMP_TX STATE 
0
 Disabled (default) 
1
 Enabled

The following sample streams are part of the system. These data streams can be routed over the audio TDM bus .

Table 7-50 TDM Limiter Gain Reduction Time Slot
GAIN_SLOT[5:0] SLOT 
0x00
 0 
0x01
 1 
...
 ... 
0x06
 6 (default) 
...
 ... 
0x3E
 62 
0x3F
 63
Table 7-51 TDM Limiter Gain Reduction Transmit Enable
GAIN_TX STATE 
0
 Disabled (default) 
1
 Enabled
Table 7-52 TDM Boost Sync Time Slot
BST_SLOT[5:0] SLOT 
0x00
 0 
0x01
 1 
...
 ... 
0x07
 7 (default) 
...
 ... 
0x3E
 62 
0x3F
 63
Table 7-53 TDM Boost Sync Enable
BST_TX STATE 
0
 Disabled (default) 
1
 Enabled

Note that the boost sync function is only operational with input sample rates higher than 16 kHz.
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