7.3.6 Power Good Pin

During turnon, the Power Good pin (PGD) is high until the voltage at VIN increases above ≊ 5 V. PGD then switches low, remaining low as the VIN voltage increases. When the voltage at OUT increases to within 1.25 V of the SENSE pin (V_DS <1.25 V), PGD switches high. PGD switches low if the V_DS of Q1 increases above 2.5 V. A pullup resistor is required at PGD as shown in Figure 20. The pullup voltage (V_PGD) can be as high as 80 V, with transient capability to 100 V, and can be higher or lower than the voltages at VIN and OUT.

Figure 20. Power Good Output

If a delay is required at PGD, suggested circuits are shown in Figure 21. In Figure 21a, capacitor C_PG adds delay to the rising edge, but not to the falling edge. In Figure 21b, the rising edge is delayed by R_PG1 + R_PG2 and C_PG, while the falling edge is delayed a lesser amount by R_PG2 and C_PG. Adding a diode across R_PG2 (Figure 21c) allows for equal delays at the two edges, or a short delay at the rising edge and a long delay at the falling edge.

Figure 21. Adding Delay to the Power Good Output Pin