ZHCSJG2A March   2019  – September 2019 TPS7A78

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      半桥配置典型原理图
      2.      全桥配置典型原理图
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Active Bridge Control
      2. 7.3.2 Full-Bridge (FB) and Half-Bridge (HB) Configurations
      3. 7.3.3 4:1 Switched-Capacitor Voltage Reduction
      4. 7.3.4 Undervoltage Lockout Circuits (VUVLO_SCIN) and (VUVLO_LDO_IN)
      5. 7.3.5 Dropout Voltage Regulation
      6. 7.3.6 Current Limit
      7. 7.3.7 Programmable Power-Fail Detection
      8. 7.3.8 Power-Good (PG) Detection
      9. 7.3.9 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Dropout Mode
      3. 7.4.3 Disabled Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Recommended Capacitor Types
      2. 8.1.2 Input and Output Capacitors Requirements
      3. 8.1.3 Startup Behavior
      4. 8.1.4 Load Transient
      5. 8.1.5 Standby Power and Output Efficiency
      6. 8.1.6 Reverse Current
      7. 8.1.7 Switched-Capacitor Stage Output Impedance
      8. 8.1.8 Power Dissipation (PD)
      9. 8.1.9 Estimating Junction Temperature
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Calculating the Cap-Drop Capacitor CS
          1. 8.2.2.1.1 CS Calculations for the Typical Design
        2. 8.2.2.2 Calculating the Surge Resistor RS
          1. 8.2.2.2.1 RS Calculations for the Typical Design
        3. 8.2.2.3 Checking for the Device Maximum ISHUNT Current
          1. 8.2.2.3.1 ISHUNT Calculations for the Typical Design
        4. 8.2.2.4 Calculating the Bulk Capacitor CSCIN
          1. 8.2.2.4.1 CSCIN Calculations for the Typical Design
        5. 8.2.2.5 Calculating the PFD Pin Resistor Dividers for a Power-Fail Detection
          1. 8.2.2.5.1 PFD Pin Resistor Divider Calculations for the Typical Design
        6. 8.2.2.6 Summary of the Typical Application Design Components
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 开发支持
        1. 11.1.1.1 评估模块
        2. 11.1.1.2 SIMPLIS 模型
      2. 11.1.2 器件命名规则
    2. 11.2 文档支持
      1. 11.2.1 相关文档
    3. 11.3 接收文档更新通知
    4. 11.4 社区资源
    5. 11.5 商标
    6. 11.6 静电放电警告
    7. 11.7 Glossary
  12. 12机械、封装和可订购信息

8.1.3 Startup Behavior

The device startup time is dependent on the circuit topology (FB versus HB configuration), AC supply voltage and frequency, input capacitors values, and output voltage. The FB configuration has a faster startup time compared to the HB configuration. Having a larger than minimum CS capacitor value shortens the startup time without exceeding the maximum ISHUNT current specified in the Recommended Operating Conditions table. However, startup behavior depends on which CSCIN and CLDO_IN capacitor values are used. Figure 19 illustrates the startup behavior with the minimum required CSCIN capacitor and a typical CLDO_IN capacitor to support 30 mA of load current with the FB configuration. Figure 20 illustrates the startup behavior with the minimum required CSCIN capacitor and a large CLDO_IN capacitor in the same configuration.

Although the load current has no effect on startup time or startup behavior, the bulk capacitor CSCIN and input capacitor CLDO_IN have a significant effect on the time and behavior; see Figure 19 and Figure 20. For some applications, larger CSCIN or CLDO_IN capacitors are used to hold-up the output voltage on for a longer period of time after the input collapses.

TPS7A78 D007_SBVS343_TPS7A78.gif
VAC = 120 VRMS at 60 Hz, FB, CS = 220 nF,
VLDO_OUT = 3.3 V, CSCIN = 47 µF, CLDO_IN = 1 µF, IOUT = 30 mA
Figure 19. Startup Behavior With a Minimum CSCIN Capacitor and a Typical CLDO_IN Capacitor for a 30-mA Load
TPS7A78 D008_SBVS343_TPS7A78.gif
VAC = 120 VRMS at 60 Hz, FB, CS = 220 nF,
VLDO_OUT = 3.3 V, CSCIN = 47 µF, CLDO_IN = 330 µF,
IOUT = 30 mA
Figure 20. Startup Behavior With a Minimum CSCIN Capacitor and a Large CLDO_IN Capacitor for a 30-mA Load
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