8.2.2.5 Calculating the PFD Pin Resistor Dividers for a Power-Fail Detection

Using the device power-fail detection feature is optional as indicated in Figure 14 and Figure 15. The PFD pin is an analog voltage input to an internal comparator that drives the open-drain PF output. The resistor divider consisting of R₁ and R₂ can be used to set the minimum V_SCIN voltage that triggers the PF output. Regardless of whether an AC or DC supply is used, the PF output triggers when the supply fails to maintain the V_SCIN voltage above V_{SCIN (MIN)}. Equation 22 gives the calculation of the R₁ – R₂ resistor divider that sets the PF pin trigger point.

Equation 23 calculates the V_{SCIN (MIN)} voltage.

Set R₁ as close as possible to the maximum value specified in the Recommended Operating Conditions table. This high R₁ value limits the power used by the resistors, then calculates the value of R₂. Choose the closest standard resistor value for R₂. Optionally, because the PFD pin is a high-impedance node, add a 10-pF capacitor in parallel with the R₂ resistors to reduce noise coupling into V_PFD.

Pull up the PF pin to a DC rail, such as V_{LDO_IN}, so that a microcontroller can monitor the PF signal as an early power-fail warning to trigger the switch to a backup power solution or to perform a controlled system shutdown. Pulling up the PF pin to V_{LDO_IN} rather than V_{LDO_OUT} ensures that the PF signal is continuously monitored even if V_{LDO_OUT} is down because of a load-transient event or a short-circuit fault.