Table 8. Switching Characteristics
VDD = 3.3 V ± 5%, VDDO = 1.5 V ± 5%, 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5% and TA = –40°C to 125°C
| PARAMETER |
TEST CONDITIONS |
MIN |
TYP |
MAX |
UNIT |
| tPDLH |
Propagation delay,
Low-to-high |
LVCMOS_CLK(1),
CLK_P/CLK_N(2) |
–40°C to 125°C |
1 |
|
2.5 |
ns |
| tSK(O) |
Output skew(3)(4) |
Measured on rising edge |
|
|
35 |
ps |
| tSK(PP) |
Part-to-part skew(4)(5) |
|
|
|
550 |
ps |
| tR/tF |
Output rise/fall time |
20% to 80%, CL= 5 pF |
100 |
310 |
600 |
ps |
| tJIT |
Additive jitter(6) |
f = 40 MHz,
Input slew rate = 1.25 V/ns,
12-kHz to 20-MHz integration band |
|
115 |
200 |
fs RMS |
| PNFLOOR |
Phase noise floor(7) |
f = 40 MHz,
Input slew rate = 1.25 V/ns |
10-kHz offset |
|
–151 |
|
dBc/Hz |
| 100-kHz offset |
|
–160 |
|
| 1-MHz offset |
|
–162 |
|
| 10-MHz offset |
|
–162 |
|
| 20-MHz offset |
|
–162 |
|
| DO |
Output duty cycle |
REF = CLK_P/CLK_N, 50% input duty cycle, f < 166 MHz |
45% |
|
55% |
| REF = LVCMOS_CLK, 50% input duty cycle, f > 166 MHz |
42% |
|
58% |
|
(1) Measured from the VDD/2 of the input to the VDDO/2 of the output.
(2) Measured from the differential input crossing point to VDDO/2 of the output.
(3) Defined as skew between outputs at the same supply voltage and with equal loading conditions. Measured at VDDO/2 of the output.
(4) Parameter is defined in accordance with JEDEC Standard 65.
(5) Calculation for part-to-part skew is the difference between the fastest and slowest tPD across multiple devices, various supply voltages, operating at the same frequency, same temperature, with equal load conditions, and using the same type of inputs on each device.
(6) Buffer additive jitter: t
JIT = SQRT(t
JIT_SYS2 – t
JIT_SOURCE2), where t
JIT_SYS is the RMS jitter of the system output (source+buffer) and t
JIT_SOURCE is the RMS jitter of the input source, and system output noise is not correlated to the input source noise. Additive jitter should be considered only when the input source noise floor is 3 dB or better than the buffer noise floor (PN
FLOOR). This is usually the case for high-quality, ultra-low-noise oscillators. Refer to
System-Level Phase Noise and Additive Jitter Measurement for input source and measurement details.
(7) Buffer phase noise floor: PN
FLOOR (dBc/Hz) = 10 × log10[10^(PN
SYSTEM/10) – 10^(PN
SOURCE/10)], where PN
SYSTEM is the phase noise floor of the system output (source+buffer) and PN
SOURCE is the phase noise floor of the input source. Buffer Phase Noise Floor should be considered only when the input source noise floor is 3 dB or better than the buffer noise floor (PN
FLOOR). This is usually the case for high-quality, ultra-low-noise oscillators. Refer to
System-Level Phase Noise and Additive Jitter Measurement for input source and measurement details.