ZHCSJG9B March   2019  – August 2019 LMK00804B-Q1

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      简化原理图
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. Table 1. Absolute Maximum Ratings
    2. Table 2. ESD Ratings
    3. Table 3. Recommended Operating Conditions
    4. Table 4. Thermal Information
    5. Table 5. Power Supply Characteristics
    6. Table 6. LVCMOS / LVTTL DC Electrical Characteristics
    7. Table 7. Differential Input DC Electrical Characteristics
    8. Table 8. Switching Characteristics
    9. Table 9. Pin Characteristics
    10. 6.1      Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Clock Enable Timing
    4. 8.4 Device Functional Modes
  9. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Output Clock Interface Circuit
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curve
          1. 9.2.1.3.1 System-Level Phase Noise and Additive Jitter Measurement
      2. 9.2.2 Input Detail
      3. 9.2.3 Input Clock Interface Circuits
    3. 9.3 Do's and Don'ts
      1. 9.3.1 Power Dissipation Calculations
      2. 9.3.2 Thermal Management
      3. 9.3.3 Recommendations for Unused Input and Output Pins
      4. 9.3.4 Input Slew Rate Considerations
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Considerations
      1. 10.1.1 Power-Supply Filtering
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Ground Planes
      2. 11.1.2 Power Supply Pins
      3. 11.1.3 Differential Input Termination
      4. 11.1.4 LVCMOS Input Termination
      5. 11.1.5 Output Termination
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 文档支持
      1. 12.1.1 相关文档
    2. 12.2 接收文档更新通知
    3. 12.3 社区资源
    4. 12.4 商标
    5. 12.5 静电放电警告
    6. 12.6 Glossary
  13. 13机械、封装和可订购信息

8.4 Device Functional Modes

The device can provide fan-out and level translation from a differential or single-ended input to a LVCMOS/LVTTL output where the output VOH and VOL levels are applied to the VDDO pin and output load condition.

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