10.2.2.8 Checking Loop Stability

The first step of circuit and stability evaluation is to look from a steady-state perspective at the following signals:

• Switching node, SW
• Inductor current, I_L
• Output ripple voltage, V_OUT(AC)

These are the basic signals that need to be measured when evaluating a switching converter. When the switching waveform shows large duty cycle jitter or the output voltage or inductor current shows oscillations, the regulation loop may be unstable. This is often a result of board layout and/or L-C combination.

As a next step in the evaluation of the regulation loop, the load transient response is tested. The time between the load transient takes place and the turn on of the PMOS switch, the output capacitor must supply all of the current required by the load. V_OUT immediately shifts by an amount equal to ΔI_(LOAD) × ESR, where ESR is the effective series resistance of C_OUT. ΔI_(LOAD) begins to charge or discharge C_OUT generating a feedback error signal used by the regulator to return V_OUT to its steady-state value. The results are most easily interpreted when the device operates in PWM mode.

During this recovery time, V_OUT can be monitored for settling time, overshoot or ringing that helps judge the converter’s stability. Without any ringing, the loop has usually more than 45°C of phase margin. Because the damping factor of the circuitry is directly related to several resistive parameters (for example, MOSFET r_DS(on)) that are temperature dependant, the loop stability analysis has to be done over the input voltage range, load current range, and temperature range.