米6体育平台手机版

ZHCSJM7 April 2019 BQ79606A-Q1

PRODUCTION DATA.

7.5 Electrical Characteristics

V_BAT = 5.5V to 30V, all LDOs operating in regulation, Typical Applications Circuit used, 3 to 6 cells connected, –40°C to +105°C free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
Supply Currents
I_SHDN	Supply current in SHUTDOWN mode	Addition of both BAT and LDOIN supply current	30	65	105	µA
I_SLP(IDLE)	Supply current in SLEEP mode with no functionality enabled	Cell balancing disabled	95	130	165	µA
I_SLP(BAL)	Supply current in SLEEP mode with only cell balancing enabled	One or more cell balancing FETs turned on	700	780	850	µA
I_ACT(IDLE)	Supply current in ACTIVE mode with no functionality enabled	No communication. Cell balancing disabled.	3.7	4.2	4.6	mA
I_ACT(COMT)	Additional supply current during communication (Average)	Daisy-chain interface communicating, transformer isolation. There is a 1KΩ termination. Depends on Transformer used.		2		mA
I_ACT(COMC)	Additional supply current during communication (Average)	Daisy-chain interface communicating, capacitor isolation. There is a 10KΩ termination.		0.5		mA
I_ACT(BAL)	Additional supply current during cell balancing	No communication. Cell balancing active.	125	145	170	µA
I_ACT(CONVERT)	Additional supply current during ADC conversion	No communication, Only Conversion Conversion started, conversion period active;	2.05	2.42	2.65	mA
Reference Voltages
V_REF1	REF1 Reference voltage	REF1 capacitor = 1 µF, AVDD in regulation, T_A = -40C to 105C	2.492	2.497	2.503	V
V_REF1SWING	Detectable REF1 amplitude during oscillations (frequency from 0.2MHz to 10MHz)	Frequency between 0.2MHz to 10MHz.		330		mV
V_REF1OV	Over-voltage threshold for REF1		2.52	2.59	2.66	V
V_REF1UV	Undervoltage threshold for REF1		2.37	2.425	2.47	V
V_REF2	REF2 reference voltage		1.0975	1.100	1.1025	V
V_REF3	Internal bandgap voltage, used by POR circuits	-40C to 105C	1.2	1.22	1.26	V
V_PTATGAIN	PTAT voltage gain	25C, AVDD_REF = 2.4V		1.17		mV/C
Supplies
V_VLDO	VLDO output voltage	I_OUT = 10 mA, C = 1 µF	4.9	5.0	5.1	V
V_VLDOOV	VLDO Over-voltage threshold		5.31	5.6	5.87	V
V_VLDOOVHYS	VLDO OV hysteresis		50	60	150	mV
I_{VLDO(LIMIT)LP}	VLDO Current limit	External allowable load on the LDO including CVDD load, C=2.2uF, SLEEP Mode.	7.9	14	23	mA
I_{VLDO(LIMIT)HP}	VLDO Current limit	External allowable load on the LDO including CVDD load, C=2.2uF, Active Mode.	21.5	35	55	mA
T_SHUT(VLDO)R	VLDO LDO thermal shutdown threshold	TJ rising		138		℃
T_SHUT(VLDO)F		TJ falling		123		℃
V_TSREF	NTC monitor reference voltage		2.47	2.5	2.53	V
I_TSREF	TSREF current limit		5		12.6	mA
V_TSREFOV	TSREF over-voltage threshold	TSREF rising,	2.7		2.85	V
V_TSREFOVHYS	TSREF over-voltage threshold hysteresis	V_TSREF falling		160		mV
V_TSREFUV	TSREF under-voltage threshold	TSREF falling,	2.16	2.22	2.27	V
V_TSREFUVHYS	TSREF under-voltage threshold hysteresis	TSREF rising	65	80	95	mV
V_OSCTSREF	Detectable voltage oscillation above V_TSREFat frequency from 0.2 MHz to 10 MHz			300		mV
V_AVDD	AVDD Output voltage	I_OUT = 8 mA, C = 2.2 µF	4.9	5.0	5.1	V
V_AVDDOV	AVDD over-voltage threshold	AVDD rising		5.7		V
V_AVDDOVHYS	AVDD OV hysteresis	AVDD falling		200		mV
V_{AVDDUV_F}	Falling AVDD under-voltage threshold	AVDD Falling	4.10		4.25	V
V_{AVDDUV_R}	Rising AVDD under-voltage threshold	AVDD Rising	4.4		4.65	V
T_SHUT(AVDD)R	AVDD LDO thermal shutdown threshold	TJ rising		138		℃
T_SHUT(AVDD)F	AVDD LDO thermal shutdown threshold	TJ falling		123		℃
V_DVDD	DVDD Output voltage	I_OUT = 8 mA, C = 2.2 µF	1.65	1.8	1.95	V
V_DVDDOV	DVDD over-voltage threshold	DVDD rising, 200mV hysteresis		2.2		V
V_{DRDVDD_F}	Falling DVDD Digital Reset threshold	DVDD falling	1.57		1.66	V
V_{DRDVDD_R}	Rising DVDD Digital Reset threshold	DVDD rising	1.67		1.77	V
T_SHUT(DVDD)R	DVDD LDO thermal shutdown threshold	TJ rising		138		℃
T_SHUT(DVDD)F	DVDD LDO thermal shutdown threshold	TJ falling		123		℃
V_{AVAO_REF_1}	Internal always-on supply rail (AVAO_REF)	Vbat>=5.5V	2.30	2.40	2.49	V
V_{AVAO_REF_2}	Internal always-on supply rail (AVAO_REF)	4.75V=<Vbat<=5.5V (Bridge devices)	2.24	2.4	2.48	V
V_{AVAO_REF_UV}	AVAO_REF under-voltage threshold	V_BAT falling, 111mV hysteresis	1.93	1.98	2.18	V
V_{AVAO_REF_OV}	AVAO_REF over-voltage threshold	V_BAT rising, 150mV hysteresis	2.75	2.85	2.95	V
V_{AVAO_REF_OVHYS}	AVAO_REF OV hysteresis	V_BAT falling		130		mV
V_{AVDDREF_FLTZ}	AVDD_REF UV threshold Falling	AVDD_REF falling, 100mV hysteresis		VAVAO-150mV		mV
V_{AVDDREF_FLTZ_HYST}	AVDD_REF UV hysteresis	AVDD_REF rising		50		mV
V_VPROG	OTP programming voltage input range		7.4	7.6	7.8	V
V_VPROGOV	VPROG overvoltage detection threshold	V_VPROG rising,	7.85	7.91	8	V
V_VPROGUV	VPROG undervoltage detection threshold	V_VPROG falling, 100mV hysteresis	7.2	7.25	7.35	V
V_VPROGUVHYS	VPROG undervoltage detection threshold hysteresis	V_VPROG rising, V_AVDD>4.5V, SH_REFL=1.1V		85		mV
V_CVDD	CVDD voltage supply input range		4.9	5	5.1	V
V_CVDDUV	CVDD under-voltage threshold	V_CVDD falling, 100-mV hysteresis	4.2	4.41	4.56	V
V_CVDDUVHYS	CVDD under-voltage threshold hysteresis			70		mV
V_VIO	IO voltage supply input range		1.8		5.25	V
V_{VIOUV_Fall}	VIO under-voltage threshold	VIO falling, 100-mV hysteresis	1.3		1.75	V
V_{VIOUV_Hys}	VIO under-voltage hysteresis threshold	VIO rising		0.1		V
V_CVSSOPEN	CVSS open detection threshold		0.092		0.26	V
_VDVSSOPEN	DVSS open detection threshold		0.092		0.26	V
CELL ADC Measurements (VC_ Inputs)
V_{C*_N}	Cell input voltage range	VCn to VCn–1, excluding VC1 to VC0, Common Mode Voltage >3V for VC3 to VC6.	–2		5.0	V
V_{C*_N}	Cell input voltage range	VC1 to VC0	0		5.0	V
ΔI_VCn	VCn to VCn–1 input current mismatch	(VCELLn - VCELLn-1) < 1V, T_A = –20°C to +65°C			990	nA
ΔI_VCn(FULL)	VCn to VCn–1 input current mismatch	-2 V < VCELL < 5 V, T_A = –40°C to +105°C			1.5	μA
V_{ACC_1}	Total channel accuracy for voltage measurements	VCELL = 3 V, CELL_ADC_CONF1[DR] = 0b11 T_A = 25°C	–1.72		0.43	mV
V_{ACC_2}	Total channel accuracy for voltage measurements	2.0 V < VCELL < 5 V, CELL_ADC_CONF1[DR] = 0b11 T_A = 0°C to +65°C	–3.23		1.91	mV
V_{ACC_3}	Total channel accuracy for voltage measurements	2.0 V < VCELL < 5 V, CELL_ADC_CONF1[DR] = 0b11 T_A = -20°C to +65°C	–4.24		2.6	mV
V_{ACC_4}	Total channel accuracy for voltage measurements	2.0 V < VCELL < 5.0 V, CELL_ADC_CONF1[DR] = 0b11 T_A = –40°C to +105°C	–4.46		3.77	mV
V_{ACC_5}	Total channel accuracy for voltage measurements	-2.0 V < VCELL < 2.0 V, CELL_ADC_CONF1[DR] = 0b11 T_A = –20°C to +65°C	–14.32		14.07	mV
V_{ACC_Full}	Total channel accuracy for voltage measurements	–2 V < VCELL < 5 V, CELL_ADC_CONF1[DR] = 0b11 T_A = –40°C to +105°C	–18.22		15.56	mV
V_RES	Resolution for voltage measurements	256 decimation ratio selected		190.7		µV
I_VCOFF	VC* leakage currents	Cell measurements disabled			0.1	µA
I_VCONADC	VC* bias currents	Cell measurement active			3	µA
Internal Temperature Sense
T_{JADC_RANGE}	TINT range		–40		125	°C
T_{JADC_RES1}	TINT resolution	CELL_ADC_CONF1[DR] = 0b00		3.3		°C
T_{JADC_RES2}	TINT resolution	CELL_ADC_CONF1[DR] = 0b11		0.125		°C
T_{JADC_ACC}	TINT temperature accuracy	CELL_ADC_CONF1[DR] = 0b11	–13		13	°C
AUX ADC Measurements
V_GPIO*	Input voltage range GPIO* to AVSS		0.0		VIO	V
V_GPIORES2	GPIO_ measurement resolution	Absolute setting, DR=256.		190.7		µV
V_ACCGP(abs)	GPIO ADC measurement accuracy in absolute measurement mode	1 V< V_{GPIO_} < 4.5 V, T_A = –40°C to +105°C, DR=256.	–13.5		+13.5	mV
V_ACCGP(rat)	GPIO ADC measurement accuracy in ratiometric measurement mode	Percentage of TSREF, T_A = –20°C to +65°C, DR=256.	–1.22		1.19	%
V_ACCGP(rat)		Percentage of TSREF, T_A = –40°C to +105°C, DR=256.	–1.28		1.23	%
V_ACCBAT	Stack voltage measurement accuracy DR=256.	VBAT>21V	-300		+300	mV
V_ACCCELL	Cell voltage AUX ADC measurement accuracy DR=256.	2 V< V_{CB_} < 5 V, T_A = –40°C to +105°C	-7.5		7.5	mV
V_{REF2_AUX}	Reference output measured by AUX, DR=256.		-17		10	mV
V_{ZERO_ACC_AUX}	Supply Rail ZERO ADC measurement accuracy, DR=256.		-25.02		18.2	mV
V_{AVAO_REF_ACC_AUX}	Supply Rail AVAO_REF ADC measurement accuracy, DR=256.		-38		35	mV
V_{REF3_ACC_AUX}	Supply Rail REF3 ADC measurement accuracy, DR=256.		-21		13.2	mV
V_{TSREF_ACC_AUX}	Supply Rail TSREF ADC measurement accuracy, DR=256.		-50.5		38	mV
V_{DVDD_ACC_AUX}	Supply Rail DVDD ADC measurement accuracy, DR=256.		-21.5		15.1	mV
V_{CVDD_ACC_AUX}	Supply Rail CVDD ADC measurement accuracy, DR=256.		-139		106.5	mV
V_{UT_ACC_AUX}	UT DAC measurement accuracy, DR=256.		-39.05		24.91	mV
V_{OT_ACC_AUX}	OT DAC measurement accuracy, DR=256.		-32.6		32.4	mV
V_{UV_ACC_AUX}	UV DAC measurement accuracy, DR=256.		-53.2		79.6	mV
V_{OV_ACC_AUX}	OV DAC measurement accuracy, DR=256.		-76.4		114.85	mV
V_{AVDD_ACC_AUX}	Supply Rail AVDD ADC measurement accuracy, DR=256.		-57.15		44.06	mV
Cell Balancing
I_BAL	Maximum balancing current with ambient temperature of 85 C	Per cell			150	mA
R_BAL	External Balancing current resistor range. The allowable range for the cell balancing resistor to set the balancing current upto 5mA to 150mA.		10		400	Ω
R_DS(ON)	Balancing FET resistance	V_CELL > 2 V	4.0	6.3	12	Ω
V_CBDONE	CBDONE threshold range for cell balancing (measured at VCn to VCn-1)	1 ≤ n ≤ 6	2.8		4.3	V
V_{CBDONEACC_1}	CBDONE threshold accuracy	-20C to 105C, 2.8V < VCELL < 4.0V	-45		45	mV
V_{CBDONEACC_1}	CBDONE threshold accuracy	-20C to 105C, 4.0V < VCELL < 4.3V	-55		55	mV
V_BAL(MIN)	Minimum cell voltage for use of internal balancing FET		2			V
I_CBOFF	CB* leakage currents	CB disabled			0.1	µA
V_CBVCFLT	CBn pin fault threshold (faulted when (CB_n-CB_n-1) / (VC_n-VC_n-1) > V_CBVCFLT	2V < V_CELL < 5V and 1 ≤ n ≤ 6	67			%
V_VCLOW	VCLOW comparator threshold for proper CBVC comparator operation VC_n-VC_n-1 > V_VCLOW	2V < Vcell < 5V and 1 ≤ n ≤ 6		0.9		V
I_OWSNK	VCn and CBn OW sink current (VC and CB =3V)	1 ≤ n ≤ 6	170	250	350	µA
I_OWSRC	VC0 and CB0 OW source current (VC and CB =0V)	n=0	200	250	350	µA
T_{SHUTCB_R}	Cell Balancing TSHUT threshold rising		123	140	155	℃
T_{SHUTCB_F}	Cell Balancing TSHUT threshold fallig			130		℃
Hardware Comparators
V_OV	OV comparator programmable range	V_CELL rising, 100 mV Hysteresis, 25-mV LSB	2		5	V
V_OVHYS	OV comparator hysteresis	V_CELL falling		100		mV
V_UV	UV comparator programmable range	V_CELL falling, 100 mV Hysteresis, 25mV LSB	0.7		3.875	V
V_UVHYS	UV comparator hysteresis	V_CELL rising		100		mV
V_OT	OT comparator programmable range	V_GPIO falling, 2% Hysteresis, 1% LSB	20		35	% of TSREF
V_OTHYS	OT comparator hysteresis	V_GPIO rising		2		% of TSREF
V_UT	UT comparator programmable range	V_GPIO rising, 2% Hysteresis, 1% LSB	60		75	% of TSREF
V_UTHYS	UT comparator hysteresis	V_GPIO falling		2		% of TSREF
V_{OVACC_1}	OV Comparator Accuracy	T_A = –20°C to 65°C, 3.8V <VCELL< 5V	–28		25	mV
V_{OVACC_2}	OV Comparator Accuracy	T_A = –40°C to 105°C, 3.8V <VCELL< 5V	–43		37	mV
V_OVACC(FULL)	OV Comparator Accuracy	T_A = –40°C to 105°C, 2V <VCELL< 5V	–75		56	mV
V_{UVACC_1}	UV Comparator Accuracy	T_A = –20°C to 65°C, 2.5V <VCELL< 3.875V	–60		40	mV
V_{UVACC_2}	UV Comparator Accuracy	T_A = –40°C to 105°C, 2.5V <VCELL< 3.875V	–70		50	mV
V_UVACC(FULL)	UV Comparator Accuracy	T_A = –40°C to 105°C, 0.7V <VCELL< 3.875V	–100		67	mV
I_CBONCOMP	CB* bias currents	Hardware comparators enabled			6	µA
V_TSCMPACC	OT/UT Comparator Accuracy		–1		1	% of TSREF
Daisy Chain Communication Bus
R_DCTX	Daisy chain transmitter output impedance			15		Ω
V_DCCM	Daisy chain common mode voltage		2.3	2.45	2.6	V
V_{COM_Tone}	Daisy-chain communication receiver threshold programmable range (V_COMP – V_COMN)	Communication tone Receiver threshold voltage (differential voltage). VBAT>5.5V.	0.66		1.96	V
V_{COM_Data}	Daisy-chain communication receiver threshold (V_COMP – V_COMN)	Communication Data Receiver threshold voltage (differential voltage). VBAT>5.5V.	0.6		1.77	V
V_{FAULTH_Tone}	Daisy-chain communication receiver threshold (V_FAULTHP – V_FAULTHN)	Fault Tone Receiver threshold voltage (differential voltage). VBAT>5.5V.	0.22		1.77	V
Digital I/Os (TX, RX, GPIO_, NFAULT, WAKEUP, SPI)
V_OH	Logic level output voltage high (TX, GPIO*, SDO)	GPIO configured as output, FET pull-up (Not Resistive) I_OUT = 1 mA, V_VIO=3.3V	VIO – 0.3			V
V_OL	Logic level output voltage low (TX, NFAULT, GPIO*, SDO)	GPIO configured as output, FET pull-down (Not resistive) I_OUT = 1 mA, V_VIO=3.3V			0.3	V
V_IH	Logic level input voltage high (RX, GPIO*, WAKEUP, SDI)	GPIO configured as input. V_VIO=3.3V	0.65xV_VIO			V
V_IL	Logic level input voltage low (RX, GPIO*, WAKEUP, SDI)	GPIO configured as input. V_VIO=3.3V			0.35xV_VIO	V
R_PUWK	Weak pullup resistor	Weak pullup selected	120	200	310	kΩ
R_PDWK	Weak pulldown resistor	Weak pulldown selected	120	200	310	kΩ
I_LKG	Input leakage	Configured as analog input for ADC application			0.1	µA
Thermal Protection
T_SD	Thermal shutdown threshold	T_DIE rising, V_BAT >= 4.75V	123	137	155	ºC
T_{SD_Fall}	Thermal shutdown falling	T_DIE falling, V_BAT >= 4.75V	108		125.5	ºC
T_WARN	Temperature warning threshold (based on temperature ADC reading)	T_DIE rising, V_BAT ≥ 4.75V		115		°C
V_PTAT	PTAT voltage at 25C	T_A=25℃		330		mV