The power-supply sequence between the IOVDD and AVDD rails can be applied in any order. However, keep the SHDNZ pin low until the IOVDD supply voltage settles to a stable and supported operating voltage range. After all supplies are stable, set the SHDNZ pin high to initialize the device.

For the supply power-up requirement, t₁ and t₂ must be at least 100 µs. For the supply power-down requirement, t₃ and t₄ must be at least 10 ms. This timing (as shown in Figure 178) allows the device to ramp down the volume on the record data, power down the analog and digital blocks, and put the device into hardware shutdown mode. The device can also be immediately put into hardware shutdown mode from active mode if SHDNZ_CFG[1:0] is set to 2'b00 using the P0_R5_D[3:2] bits. In that case, t₃ and t₄ are required to be at least 100 µs.

Figure 178. Power-Supply Sequencing Requirement Timing Diagram

Make sure that the supply ramp rate is slower than 1 V/µs and that the wait time between a power-down and a power-up event is at least 100 ms.

After releasing SHDNZ, or after a software reset, delay any additional I²C or SPI transactions to the device for at least 2 ms to allow the device to initialize the internal registers. See the Device Functional Modes section for details on how the device operates in various modes after the device power supplies are settled to the recommended operating voltage levels.

The TLV320ADC6140 supports a single AVDD supply operation by integrating an on-chip digital regulator, DREG, and an analog regulator, AREG. However, if the AVDD voltage is less than 1.98 V in the system, then short the AREG and AVDD pins onboard and do not enable the internal AREG by keeping the AREG_SELECT bit to 1b'0 (default value) of P0_R2. If the AVDD supply used in the system is higher than 2.7 V, then the host device can set AREG_SELECT to 1'b1 while exiting sleep mode to allow the device internal regulator to generate the AREG supply.