ZHCSK90D september 2019 – january 2021 UCC12050
PRODUCTION DATA
To design using UCC12050, a few simple design considerations must be evaluated. Table 8-1 shows some recommended values for a typical application. See Section 9 and Section 10 sections to review other key design considerations for the UCC12050.
| PARAMETER | RECOMMENDED VALUE |
|---|---|
| Input supply voltage, VINP | 4.5 V to 5.5 V |
| Decoupling capacitance between VINP and GNDP | 10 µF, 16 V, ± 10%, X7R |
| Decoupling capacitance between VISO and GNDS (1) | 10 µF, 16 V, ± 10%, X7R |
| Optional additional capacitance on VISO or VINP to reduce high-frequency ripple | 0.1 µF, 50 V,± 10%, X7R |
| Pull-up resistor from SYNC_OK to VINP, RPU | 100 kΩ |
| Pull-up resistor from SEL to VISO for 5.0V output voltage mode, RSEL | 0 Ω |
| Pull-up resistor from SEL to VISO for 5.4V output voltage mode, RSEL | 100 kΩ |
| Optional SYNC signal impedance-matching resistor, RSYNC | Match source — typical values are 50 Ω, 75 Ω, 100 Ω, or 1 kΩ |
| External clock signal applied on SYNC | 16 MHz |