In the applications of traction inverter or motor drive, the power semiconductors are in hard switching mode. With the strong drive strength of the UCC21750-Q1, the dV/dt can be high, especially for SiC MOSFET. Noise cannot only be coupled to the gate voltage due to the parasitic inductance, but also to the input side as the non-ideal PCB layout and coupled capacitance.

The UCC21750-Q1 features a 40-ns internal deglitch filter to IN+, IN– and RST/EN pin. Any signal less than 40 ns can be filtered out from the input pins. For noisy systems, external low-pass filter can be added externally to the input pins. Adding low-pass filters to IN+, IN– and RST/EN pins can effectively increase the noise immunity and increase the signal integrity. When not in use, the IN+, IN– and RST/EN pins must not be floating. IN– must be tied to GND if only IN+ is used for non-inverting input to output configuration. The purpose of the low-pass filter is to filter out the high frequency noise generated by the layout parasitics. While choosing the low-pass filter resistors and capacitors, both the noise immunity effect and delay time must be considered according to the system requirements.